Vinay Saripalli

According to our database, Vinay Saripalli authored at least 15 papers between 2008 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

CDLS: Constraint Driven Generative AI Framework for Analog Layout Synthesis.

Prasanth Mangalagiri, Lynn Qian, Farrukh Zafar, Praveen Mosalikanti, Phoebe Chang, Arun Kurian, Vinay Saripalli

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2013

Steep-Slope Devices: From Dark to Dim Silicon.

Karthik Swaminathan, Emre Kultursay, Vinay Saripalli, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Suman Datta

IEEE Micro, 2013

Design of energy-efficient circuits and systems using tunnel field effect transistors.

Ravindhiran Mukundrajan, Matthew Cotter, Sungmin Bae, Vinay Saripalli, Mary Jane Irwin, Suman Datta, Vijaykrishnan Narayanan

IET Circuits Devices Syst., 2013

2012

Ultra Low Power Circuit Design Using Tunnel FETs.

Ravindhiran Mukundrajan, Matthew Cotter, Vinay Saripalli, Mary Jane Irwin, Suman Datta, Vijaykrishnan Narayanan

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Design space exploration of workload-specific last-level caches.

Karthik Swaminathan, Emre Kultursay, Vinay Saripalli, Vijaykrishnan Narayanan, Mahmut T. Kandemir

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Performance enhancement under power constraints using heterogeneous CMOS-TFET multicores.

Emre Kultursay, Karthik Swaminathan, Vinay Saripalli, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Suman Datta

Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011

Exploiting Heterogeneity for Energy Efficiency in Chip Multiprocessors.

Vinay Saripalli, Guangyu Sun, Asit K. Mishra, Yuan Xie, Suman Datta, Vijaykrishnan Narayanan

IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design.

Vinay Saripalli, Suman Datta, Vijaykrishnan Narayanan, Jaydeep P. Kulkarni

Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Improving energy efficiency of multi-threaded applications using heterogeneous CMOS-TFET multicores.

Karthik Swaminathan, Emre Kultursay, Vinay Saripalli, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Suman Datta

Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Enabling architectural innovations using non-volatile memory.

Vijaykrishnan Narayanan, Vinay Saripalli, Karthik Swaminathan, Ravindhiran Mukundrajan, Guangyu Sun, Yuan Xie, Suman Datta

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores.

Vinay Saripalli, Asit K. Mishra, Suman Datta, Vijaykrishnan Narayanan

Proceedings of the 48th Design Automation Conference, 2011

2010

Energy-Delay Performance of Nanoscale Transistors Exhibiting Single Electron Behavior and Associated Logic Circuits.

Vinay Saripalli, Lu Liu, Suman Datta, Vijaykrishnan Narayanan

J. Low Power Electron., 2010

Analyzing Energy-Delay Behavior in Room Temperature Single Electron Transistors.

Vinay Saripalli, Vijaykrishnan Narayanan, Suman Datta

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

2009

Ultra Low Energy Binary Decision Diagram Circuits Using Few Electron Transistors.

Vinay Saripalli, Vijaykrishnan Narayanan, Suman Datta

Proceedings of the Nano-Net - 4th International ICST Conference, 2009

2008

Reconfigurable BDD based quantum circuits.

Soumya Eachempati, Vinay Saripalli, Narayanan Vijaykrishnan, Suman Datta

Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures, 2008