Vinay Rayapati

According to our database, Vinay Rayapati authored at least 7 papers between 2023 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

EBACA: Efficient Bfloat16-based Activation Function Implementation Using Enhanced CORDIC Architecture.

Vinay Rayapati, Sanampudi Gopala Krishna Reddy, Gandi Ajay Kumar, Gogireddy Ravi Kiran Reddy, Madhav Rao

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

Clustering-Based-Approach for Hardware Implementation of Activation Functions.

Mahati Basavaraju, Omkar Girish Ratnaparkhi, Vinay Rayapati, Madhav Rao

Proceedings of the 37th IEEE International System-on-Chip Conference, 2024

Exploring Hardware Activation Function Design: CORDIC Architecture in Diverse Floating Formats.

Mahati Basavaraju, Vinay Rayapati, Madhav Rao

Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

FPGA-based Hardware Software Co-design to Accelerate Brain Tumour Segmentation.

Vinay Rayapati, Gogireddy Ravi Kiran Reddy, Gandi Ajay Kumar, Saketh Gajawada, Sanampudi Gopala Krishna Reddy, Nanditha Rao

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

VPU-CIM: A 130nm, 33.98 TOPS/W RRAM based Compute-In-Memory Vector Co-Processor.

Chithambara Moorthii J, Vinay Rayapati, Nanditha Rao, Manan Suri

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

POCO: Hardware Characterization of Activation Functions using POSIT-CORDIC Architecture.

Mahati Basavaraju, Vinay Rayapati, Madhav Rao

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023

High Performance and Energy Efficient AMD and BWAD Pooling Schemes Characterised for CNN Accelerators.

Vinay Rayapati, Mahati Basavaraju, Madhav Rao

Proceedings of the 26th Euromicro Conference on Digital System Design, 2023