Vinay K. Chippa

According to our database, Vinay K. Chippa authored at least 11 papers between 2010 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2014

Scalable Effort Hardware Design.

Vinay Kumar Chippa, Debabrata Mohapatra, Kaushik Roy, Srimat T. Chakradhar, Anand Raghunathan

IEEE Trans. Very Large Scale Integr. Syst., 2014

StoRM: a stochastic recognition and mining processor.

Vinay K. Chippa, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan

Proceedings of the International Symposium on Low Power Electronics and Design, 2014

2013

Managing the Quality vs. Efficiency Trade-off Using Dynamic Effort Scaling.

Vinay K. Chippa, Kaushik Roy, Srimat T. Chakradhar, Anand Raghunathan

ACM Trans. Embed. Comput. Syst., 2013

Quality programmable vector processors for approximate computing.

Swagath Venkataramani, Vinay K. Chippa, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan

Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

Analysis and characterization of inherent application resilience for approximate computing.

Vinay K. Chippa, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Energy-efficient recognition and mining processor using scalable effort design.

Vinay K. Chippa, Hrishikesh Jayakumar, Debabrata Mohapatra, Kaushik Roy, Anand Raghunathan

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

Approximate computing: An integrated hardware approach.

Vinay K. Chippa, Swagath Venkataramani, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan

Proceedings of the 2013 Asilomar Conference on Signals, 2013

2011

Energy efficient many-core processor for recognition and mining using spin-based memory.

Rangharajan Venkatesan, Vinay K. Chippa, Charles Augustine, Kaushik Roy, Anand Raghunathan

Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Design of voltage-scalable meta-functions for approximate computing.

Debabrata Mohapatra, Vinay K. Chippa, Anand Raghunathan, Kaushik Roy

Proceedings of the Design, Automation and Test in Europe, 2011

Dynamic effort scaling: managing the quality-efficiency tradeoff.

Vinay K. Chippa, Anand Raghunathan, Kaushik Roy, Srimat T. Chakradhar

Proceedings of the 48th Design Automation Conference, 2011

2010

Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency.

Vinay K. Chippa, Debabrata Mohapatra, Anand Raghunathan, Kaushik Roy, Srimat T. Chakradhar

Proceedings of the 47th Design Automation Conference, 2010