Vinay C. Patil

According to our database, Vinay C. Patil authored at least 25 papers between 2011 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2022

Realizing Robust, Lightweight Strong PUFs for Securing Smart Grids.

Vinay C. Patil, Sandip Kundu

IEEE Trans. Consumer Electron., 2022

Combination Frequency Differencing for Identifying Design Weaknesses in Physical Unclonable Functions.

D. Richard Kuhn, M. S. Raunak, Charles B. Prado, Vinay C. Patil, Raghu N. Kacker

Proceedings of the 15th IEEE International Conference on Software Testing, 2022

2021

Preventing DNN Model IP Theft via Hardware Obfuscation.

Brunno F. Goldstein, Vinay C. Patil, Victor da Cruz Ferreira, Alexandre Solon Nery, Felipe M. G. França, Sandip Kundu

IEEE J. Emerg. Sel. Topics Circuits Syst., 2021

2020

On Leveraging Multi-threshold FinFETs for Design Obfuscation.

Vinay C. Patil, Sandip Kundu

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

2019

Design of Robust, High-Entropy Strong PUFs via Weightless Neural Network.

Leandro Santiago de Araújo, Vinay C. Patil, Charles B. Prado, Tiago A. O. Alves, Leandro A. J. Marzulo, Felipe M. G. França, Sandip Kundu

J. Hardw. Syst. Secur., 2019

Efficient Testing of Physically Unclonable Functions for Uniqueness.

Leandro Santiago de Araújo, Vinay C. Patil, Leandro Augusto Justen Marzulo, Felipe Maia Galvão França, Sandip Kundu

Proceedings of the 28th IEEE Asian Test Symposium, 2019

2018

On Enhancing Reliability of Weak PUFs via Intelligent Post-Silicon Accelerated Aging.

Md. Nazmul Islam, Vinay C. Patil, Sandip Kundu

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

On IC traceability via blockchain.

Md. Nazmul Islam, Vinay C. Patil, Sandip Kundu

Proceedings of the 2018 International Symposium on VLSI Design, 2018

Defeating Strong PUF Modeling Attack via Adverse Selection of Challenge-Response Pairs.

Horacio L. França, Charles B. Prado, Vinay C. Patil, Sandip Kundu

Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2018

2017

Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device and Logic-Level Techniques.

Arunkumar Vijayakumar, Vinay C. Patil, Daniel E. Holcomb, Christof Paar, Sandip Kundu

IEEE Trans. Inf. Forensics Secur., 2017

Peer pressure on identity: On requirements for disambiguating PUFs in noisy environment.

Pavithra Ramesh, Vinay C. Patil, Sandip Kundu

Proceedings of the 2017 IEEE North Atlantic Test Workshop, 2017

Determining proximal geolocation of IoT edge devices via covert channel.

Md. Nazmul Islam, Vinay C. Patil, Sandip Kundu

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

A guide to graceful aging: How not to overindulge in post-silicon burn-in for enhancing reliability of weak PUF.

Md. Nazmul Islam, Vinay C. Patil, Sandip Kundu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Improving reliability of weak PUFs via circuit techniques to enhance mismatch.

Vinay C. Patil, Arunkumar Vijayakumar, Daniel E. Holcomb, Sandip Kundu

Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

Realizing strong PUF from weak PUF via neural computing.

Leandro Santiago, Vinay C. Patil, Charles B. Prado, Tiago A. O. Alves, Leandro A. J. Marzulo, Felipe M. G. França, Sandip Kundu

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

2016

An Efficient Method for Clock Skew Scheduling to Reduce Peak Current.

Arunkumar Vijayakumar, Vinay C. Patil, Sandip Kundu

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

On testing physically unclonable functions for uniqueness.

Arunkumar Vijayakumar, Vinay C. Patil, Sandip Kundu

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Preventing integrated circuit piracy via custom encoding of hardware instruction set.

Vinay C. Patil, Arunkumar Vijayakumar, Sandip Kundu

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Machine learning resistant strong PUF: Possible or a pipe dream?

Arunkumar Vijayakumar, Vinay C. Patil, Charles B. Prado, Sandip Kundu

Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016

On meta-obfuscation of physical layouts to conceal design characteristics.

Vinay C. Patil, Arunkumar Vijayakumar, Sandip Kundu

Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

2014

On Maximizing Decoupling Capacitance of Clock-Gated Logic for Robust Power Delivery.

Arunkumar Vijayakumar, Vinay C. Patil, Sandip Kundu

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

On pattern generation for maximizing IR drop.

Arunkumar Vijayakumar, Vinay C. Patil, Girish Paladugu, Sandip Kundu

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

2013

Impact of Clock-Gating on Power Distribution Network Using Wavelet Analysis.

Vinay C. Patil, Sudarshan Srinivasan, Wayne P. Burleson, Sandip Kundu

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

2012

On Design of Temperature Invariant Physically Unclonable Functions Based on Ring Oscillators.

Raghavan Kumar, Vinay C. Patil, Sandip Kundu

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

2011

Design of Unique and Reliable Physically Unclonable Functions Based on Current Starved Inverter Chain.

Raghavan Kumar, Vinay C. Patil, Sandip Kundu

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011