Vinay Bhaskar Chandratre

According to our database, Vinay Bhaskar Chandratre authored at least 4 papers between 2008 and 2011.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2011

Extraction of Aspect Ratio for Non-Manhattan CMOS Devices.

Shiv Kumar, Vinay Bhaskar Chandratre, Sudheer K. Mohammed, C. K. Pithawa

Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

500 MHz Delay Locked Loop Based 128-bin, 256 ns Deep Analog Memory ASIC "Anusmriti".

Menka Sukhwani, Vinay Bhaskar Chandratre, Megha Thomas, C. K. Pithawa, Vangmayee Sharda

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

2010

An Improved High Resolution CMOS Timing Generator Using Array of Digital Delay Lock Loops.

Balaji Srinivasan, Vinay Bhaskar Chandratre

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

2008

0.35µ, 1 GHz, CMOS Timing Generator Using Array of Digital Delay Lock Loops.

Balaji Srinivasan, Vinay Bhaskar Chandratre, Menka Tewani

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008