Vinay B. Y. Kumar

According to our database, Vinay B. Y. Kumar authored at least 18 papers between 2010 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

AERO: Design Space Exploration Framework for Resource-Constrained CNN Mapping on Tile-Based Accelerators.

Simei Yang, Debjyoti Bhattacharjee, Vinay B. Y. Kumar, Saikat Chatterjee, Sayandip De, Peter Debacker, Diederik Verkest, Arindam Mallik, Francky Catthoor

IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

2021

Feeding Three Birds With One Scone: A Generic Duplication Based Countermeasure To Fault Attacks.

Anubhab Baksi, Shivam Bhasin, Jakub Breier, Anupam Chattopadhyay, Vinay B. Y. Kumar

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Towards Designing a Secure RISC-V System-on-Chip: ITUS.

Vinay B. Y. Kumar, Suman Deb, Naina Gupta, Shivam Bhasin, Jawad Haj-Yahya, Anupam Chattopadhyay, Avi Mendelson

J. Hardw. Syst. Secur., 2020

A Novel Duplication Based Countermeasure To Statistical Ineffective Fault Analysis.

Anubhab Baksi, Vinay B. Y. Kumar, Banashri Karmakar, Shivam Bhasin, Dhiman Saha, Anupam Chattopadhyay

IACR Cryptol. ePrint Arch., 2020

Feeding Three Birds With One Scone: A Generic Duplication Based Countermeasure To Fault Attacks (Extended Version).

Anubhab Baksi, Shivam Bhasin, Jakub Breier, Anupam Chattopadhyay, Vinay B. Y. Kumar

IACR Cryptol. ePrint Arch., 2020

Secure Your SoC: Building System-an-Chip Designs for Security.

Shivam Bhasin, Trevor E. Carlson, Anupam Chattopadhyay, Vinay B. Y. Kumar, Avi Mendelson, Romain Poussier, Yaswanth Tavva

Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020

Post-Quantum Secure Boot.

Vinay B. Y. Kumar, Naina Gupta, Anupam Chattopadhyay, Michael Kasper, Christoph Krauß, Ruben Niederhagen

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

ITUS: A Secure RISC-V System-on-Chip.

Vinay B. Y. Kumar, Anupam Chattopadhyay, Jawad Haj-Yahya, Avi Mendelson

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

Recruiting Fault Tolerance Techniques for Microprocessor Security.

Vinay B. Y. Kumar, Suman Deb, Rupesh Kumar, Mustafa Khairallah, Anupam Chattopadhyay, Avi Mendelson

Proceedings of the 28th IEEE Asian Test Symposium, 2019

2018

Lightweight Forth Programmable NoCs.

Vinay B. Y. Kumar, Deval Shah, Mandar Datar, Sachin B. Patkar

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

2016

Relaxation Based Circuit Simulation Acceleration over CPU-FPGA.

Vinay B. Y. Kumar, Kulshreshth Dhiman, Mandar Datar, Akash Pacharne, H. Narayanan, Sachin B. Patkar

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

2015

Framework for Application Mapping over Packet-Switched Network of FPGAs: Case Studies.

Vinay B. Y. Kumar, Pinalkumar Engineer, Mandar Datar, Yatish Turakhia, Saurabh Agarwal, Sanket Diwale, Sachin B. Patkar

CoRR, 2015

Parallel two step random walk algorithm to analyze VLSI power grid networks.

Satyabrata Dash, Vivek Bangera, Vinay B. Y. Kumar, Gaurav Trivedi, Sachin B. Patkar

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

2014

Projective Geometry and precedence constraint based application mapping on multicore network-on-chip systems.

Janak Porwal, Sanket Diwale, Vinay B. Y. Kumar, Sachin B. Patkar

Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

FPGA-based implementation of M4RM for matrix multiplication over GF(2).

Vivek Kumar, Vinay B. Y. Kumar, Sachin B. Patkar

Proceedings of the 18th International Symposium on VLSI Design and Test, 2014

Storage-allocation to sequential structures in High-Level Synthesis-assisted prototyping.

Vinay B. Y. Kumar, Shovan Maity, Sachin B. Patkar

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013

Hardware-software Scalable Architectures for Gaussian Elimination over GF(2) and Higher Galois Fields.

Prateek Saxena, Vinay B. Y. Kumar, Dilawar Singh, H. Narayanan, Sachin B. Patkar

Proceedings of the PECCS 2013, 2013

2010

FPGA Based High Performance Double-Precision Matrix Multiplication.

Vinay B. Y. Kumar, Siddharth Joshi, Sachin B. Patkar, H. Narayanan

Int. J. Parallel Program., 2010