Vili Viitamäki

Orcid: 0000-0002-6034-5655

Affiliations:

Tampere University of Technology, Laboratory of Pervasive Computing, Finland

According to our database¹, Vili Viitamäki authored at least 6 papers between 2017 and 2019.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of five.

Timeline

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Book

In proceedings

Article

PhD thesis

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Bibliography

2019

Feasibility of FPGA accelerated IPsec on cloud.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2019

2018

Live Demonstration: 4K100p HEVC Intra Encoder.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

FPGA-Powered 4K120p HEVC Intra Encoder.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

Kvazaar 4K HEVC intra encoder on FPGA accelerated airframe server.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

High-level synthesized 2-D IDCT/IDST implementation for HEVC codecs on FPGA.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

High-level synthesis implementation of HEVC 2-D DCT/DST on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Conference on Acoustics, 2017

Vili Viitamäki

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Bibliography

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