Vikramkumar Pudi

Orcid: 0000-0003-3992-0624

According to our database1, Vikramkumar Pudi authored at least 30 papers between 2015 and 2024.

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Bibliography

2024
Image Compression Based on Near Lossless Predictive Measurement Coding for Block-Based Compressive Sensing.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2024

Redefining Clock Network Construction: The Nested Flex Paradigm for Enhanced PPA Dynamics.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
Design of Energy Efficient and Low Delay Posit Multiplier.
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

Design of Low Power ALU for RISC-VISA.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023

A Configurable Multi Source Clock Tree Synthesis For High Frequency Network On Chips.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Harnessing Hybrid Clock Tree Topology to Boost PPA in Highly Utilized Designs.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023

2022
A Novel In-Memory Wallace Tree Multiplier Architecture Using Majority Logic.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Inner Product Computation In-Memory Using Distributed Arithmetic.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Hardware Implementation of SpoC-128.
IACR Cryptol. ePrint Arch., 2022

2021
Design of Energy-Efficient TSPC based D Flip-flop for CNTFET Technology.
Proceedings of the 25th International Symposium on VLSI Design and Test, 2021

Design of Low Area and Low Power Systolic Serial Parallel Multiplier using CNTFETs.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021

2020
A Brain-Computer Interface Framework Based on Compressive Sensing and Deep Learning.
IEEE Consumer Electron. Mag., 2020

Cyber Security Protocol for Secure Traffic Monitoring Systems using PUF-based Key Management.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2020

2019
New Majority Gate-Based Parallel BCD Adder Designs for Quantum-Dot Cellular Automata.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Hardware Efficient NIPALS Architecture for Principal Component Analysis of Hyper Spectral Images.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

Lightweight Secure-Boot Architecture for RISC-V System-on-Chip.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

2018
Secure and Lightweight Compressive Sensing Using Stream Cipher.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Security Vulnerabilities of Unmanned Aerial Vehicles and Countermeasures: An Experimental Study.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Lightweight and High Performance SHA-256 using Architectural Folding and 4-2 Adder Compressor.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

An FPGA-Based Brain Computer Interfacing Using Compressive Sensing and Machine Learning.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Lightweight ASIC Implementation of AEGIS-128.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Efficient and Lightweight Quantized Compressive Sensing using μ-Law.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

CoLPUF : A Novel Configurable LFSR-based PUF.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity.
IEEE Trans. Computers, 2017

Approximate compressed sensing for hardware-efficient image compression.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

SHA-3 implementation using ReRAM based in-memory computing architecture.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

2016
FPGA Based Cyber Security Protocol for Automated Traffic Monitoring Systems: Proposal and Implementation.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Modified projected Landweber method for Compressive-Sensing reconstruction of images with non-orthogonal matrices.
Proceedings of the International Symposium on Integrated Circuits, 2016

2015
A Bit-Serial Pipelined Architecture for High-Performance DHT Computation in Quantum-Dot Cellular Automata.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Very large-scale integration architecture for video stabilisation and implementation on a field programmable gate array-based autonomous vehicle.
IET Comput. Vis., 2015


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