Vikramkumar Pudi

According to our database, Vikramkumar Pudi authored at least 30 papers between 2015 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Image Compression Based on Near Lossless Predictive Measurement Coding for Block-Based Compressive Sensing.

K. Lakshmi BhanuPrakash Reddy, Vikramkumar Pudi, Balasubramanyam Appina, Anupam Chattopadhyay

IEEE Trans. Circuits Syst. II Express Briefs, May, 2024

Redefining Clock Network Construction: The Nested Flex Paradigm for Enhanced PPA Dynamics.

Lakshmi Sarvaani P, Subba Ramkumar Reddy Annapalli, Vikramkumar Pudi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023

Design of Energy Efficient and Low Delay Posit Multiplier.

K. Lakshmi BhanuPrakash Reddy, Haripriya R. S, Keerthija Puli, Subba Ramkumar Reddy Annapalli, Vikramkumar Pudi

Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

Design of Low Power ALU for RISC-VISA.

Keerthija Puli, Vikramkumar Pudi

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023

A Configurable Multi Source Clock Tree Synthesis For High Frequency Network On Chips.

Lakshmi Sarvaani P, Subba Ramkumar Reddy Annapalli, Vikramkumar Pudi, Naga Teja Babu M

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Harnessing Hybrid Clock Tree Topology to Boost PPA in Highly Utilized Designs.

Lakshmi Sarvaani P, Subba Ramkumar Reddy Annapalli, Vikramkumar Pudi

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023

2022

A Novel In-Memory Wallace Tree Multiplier Architecture Using Majority Logic.

Vijaya Lakshmi, John Reuben, Vikramkumar Pudi

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Inner Product Computation In-Memory Using Distributed Arithmetic.

Vijaya Lakshmi, Vikramkumar Pudi, John Reuben

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Hardware Implementation of SpoC-128.

Ambati Sathvik, Tirunagari Rahul, Anubhab Baksi, Vikramkumar Pudi

IACR Cryptol. ePrint Arch., 2022

2021

Design of Energy-Efficient TSPC based D Flip-flop for CNTFET Technology.

K. Lakshmi BhanuPrakash Reddy, K. B. Dheeraj Kumar, Vikramkumar Pudi

Proceedings of the 25th International Symposium on VLSI Design and Test, 2021

Design of Low Area and Low Power Systolic Serial Parallel Multiplier using CNTFETs.

K. B. Dheeraj Kumar, K. Lakshmi BhanuPrakash Reddy, Vikramkumar Pudi, Srinivasu Bodapati

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021

2020

A Brain-Computer Interface Framework Based on Compressive Sensing and Deep Learning.

Ritu Ranjan Shrivastwa, Vikramkumar Pudi, Duo Chen, Rosa Q. So, Anupam Chattopadhyay, Cuntai Guan

IEEE Consumer Electron. Mag., 2020

Cyber Security Protocol for Secure Traffic Monitoring Systems using PUF-based Key Management.

Vikramkumar Pudi, Srinivasu Bodapati, Sachin Kumar, Anupam Chattopadhyay

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2020

2019

New Majority Gate-Based Parallel BCD Adder Designs for Quantum-Dot Cellular Automata.

Tingting Zhang, Vikramkumar Pudi, Weiqiang Liu

IEEE Trans. Circuits Syst. II Express Briefs, 2019

Hardware Efficient NIPALS Architecture for Principal Component Analysis of Hyper Spectral Images.

Sai Praveen Kadiyala, Vikram Kumar Pudi, Mohit Garg, Hau T. Ngo, Siew-Kei Lam, Thambipillai Srikanthan

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

Lightweight Secure-Boot Architecture for RISC-V System-on-Chip.

Jawad Haj-Yahya, Ming Ming Wong, Vikramkumar Pudi, Shivam Bhasin, Anupam Chattopadhyay

Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

2018

Secure and Lightweight Compressive Sensing Using Stream Cipher.

Vikramkumar Pudi, Anupam Chattopadhyay, Kwok-Yan Lam

IEEE Trans. Circuits Syst. II Express Briefs, 2018

Security Vulnerabilities of Unmanned Aerial Vehicles and Countermeasures: An Experimental Study.

Vishal Dey, Vikramkumar Pudi, Anupam Chattopadhyay, Yuval Elovici

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Lightweight and High Performance SHA-256 using Architectural Folding and 4-2 Adder Compressor.

Ming Ming Wong, Vikramkumar Pudi, Anupam Chattopadhyay

Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

An FPGA-Based Brain Computer Interfacing Using Compressive Sensing and Machine Learning.

Ritu Ranjan Shrivastwa, Vikramkumar Pudi, Anupam Chattopadhyay

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Lightweight ASIC Implementation of AEGIS-128.

Anubhab Baksi, Vikramkumar Pudi, Swagata Mandal, Anupam Chattopadhyay

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Efficient and Lightweight Quantized Compressive Sensing using μ-Law.

Vikramkumar Pudi, Anupam Chattopadhyay, Kwok-Yan Lam

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

CoLPUF : A Novel Configurable LFSR-based PUF.

B. Srinivasu, Vikramkumar Pudi, Anupam Chattopadhyay, Kwok-Yan Lam

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017

Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity.

Vikramkumar Pudi, K. Sridharan, Fabrizio Lombardi

IEEE Trans. Computers, 2017

Approximate compressed sensing for hardware-efficient image compression.

Sai Praveen Kadiyala, Vikram Kumar Pudi, Siew-Kei Lam

Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

SHA-3 implementation using ReRAM based in-memory computing architecture.

Debjyoti Bhattacharjee, Vikramkumar Pudi, Anupam Chattopadhyay

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

2016

FPGA Based Cyber Security Protocol for Automated Traffic Monitoring Systems: Proposal and Implementation.

Anupam Chattopadhyay, Vikramkumar Pudi, Anubhab Baksi, Thambipillai Srikanthan

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Modified projected Landweber method for Compressive-Sensing reconstruction of images with non-orthogonal matrices.

Vikramkumar Pudi, Anupam Chattopadhyay, Thambipillai Srikanthan

Proceedings of the International Symposium on Integrated Circuits, 2016

2015

A Bit-Serial Pipelined Architecture for High-Performance DHT Computation in Quantum-Dot Cellular Automata.

Vikramkumar Pudi, K. Sridharan

IEEE Trans. Very Large Scale Integr. Syst., 2015

Very large-scale integration architecture for video stabilisation and implementation on a field programmable gate array-based autonomous vehicle.

Tahiyah Nou Shene, Vikramkumar Pudi, K. Sridharan, Vineetha Thomas, J. Arthi

IET Comput. Vis., 2015