Vikas Rana

According to our database, Vikas Rana authored at least 49 papers between 2012 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Employing Vector Field Techniques on the Analysis of Memristor Cellular Nonlinear Networks Cell Dynamics.

Chandan Singh, Vasileios G. Ntinas, Dimitrios A. Prousalis, Yongmin Wang, Ahmet Samil Demirkol, Ioannis Messaris, Vikas Rana, Stephan Menzel, Alon Ascoli, Ronald Tetzlaff

CoRR, 2024

Harnessing Entropy: RRAM Crossbar-based Unified PUF and RNG.

Gokulnath Rajendran, Furqan Zahoor, Sidhaant Sachin Thakker, Simranjeet Singh, Farhad Merchant, Vikas Rana, Anupam Chattopadhyay

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array.

Ankit Bende, Simranjeet Singh, Chandan Kumar Jha, Tim Kempen, Felix Cüppers, Christopher Bengel, Andre Zambanini, Dennis Nielinger, Sachin B. Patkar, Rolf Drechsler, Rainer Waser, Farhad Merchant, Vikas Rana

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

In-Memory Mirroring: Cloning Without Reading.

Simranjeet Singh, Ankit Bende, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Sachin B. Patkar, Farhad Merchant

Proceedings of the 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024

Experimental Evidence for Local Fading Memory Effects in TaOx ReRAM Cells.

Nicolas Schmitt, Ioannis Messaris, Ahmet Samil Demirkol, Vasileios G. Ntinas, Dimitrios A. Prousalis, Ronald Tetzlaff, Alon Ascoli, Fernando Corinto, Marco Gilli, S. Zhang, Stephan Menzel, Vikas Rana, Leon O. Chua

Proceedings of the IEEE International Conference on Metrology for eXtended Reality, 2024

Error Detection and Correction Codes for Safe In-Memory Computations.

Luca Parrini, Taha Soliman, Benjamin Hettwer, Jan Micha Borrmann, Simranjeet Singh, Ankit Bende, Vikas Rana, Farhad Merchant, Norbert Wehn

Proceedings of the IEEE European Test Symposium, 2024

MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory.

Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023

Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style.

Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Phrangboklang Lyngton Thangkhiew, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant

IEEE Embed. Syst. Lett., December, 2023

A Study of the Electroforming Process in 1T1R Memory Arrays.

Seokki Son, Camilla La Torre, Andreas Kindsmüller, Vikas Rana, Stephan Menzel

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023

PR-PUF: A Reconfigurable Strong RRAM PUF.

Gokulnath Rajendran, Furqan Zahoor, Simranjeet Singh, Farhad Merchant, Vikas Rana, Anupam Chattopadhyay

Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023

A Simplified Variability-Aware VCM Memristor Model for Efficient Circuit Simulation.

Vasileios G. Ntinas, Dharmik Patel, Yongmin Wang, Ioannis Messaris, Vikas Rana, Stephan Menzel, Alon Ascoli, Ronald Tetzlaff

Proceedings of the 19th International Conference on Synthesis, 2023

Integrated Architecture for Neural Networks and Security Primitives using RRAM Crossbar.

Simranjeet Singh, Furqan Zahoor, Gokulnath Rajendran, Vikas Rana, Sachin B. Patkar, Anupam Chattopadhyay, Farhad Merchant

Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Finite State Automata Design using 1T1R ReRAM Crossbar.

Simranjeet Singh, Omar Ghazal, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Rishad A. Shafik, Alex Yakovlev, Sachin B. Patkar, Farhad Merchant

Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Experimental Verification of Uncoupled Memristive Cellular Nonlinear Network by Processing the EDGE Detection Task.

Yongmin Wang, Kristoffer Schnieders, Vasileios G. Ntinas, Alon Ascoli, Felix Cüppers, Susanne Hoffmann-Eifert, Stefan Wiefels, Ronald Tetzlaff, Vikas Rana, Stephan Menzel

Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023

Exploring Multi-Valued Logic and its Application in Emerging Post-CMOS Technologies.

Simranjeet Singh, Elmira Moussavi, Christopher Bengel, Sachin B. Patkar, Rainer Waser, Rainer Leupers, Vikas Rana, Vivek Pachauri, Stephan Menzel, Farhad Merchant

Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023

Exploration of Bistable Oscillatory Dynamics in a Memristor from Forschungszentrum Jülich.

Nicolas Schmitt, Alon Ascoli, Ioannis Messaris, Ahmet Samil Demirkol, Vasileios G. Ntinas, Dimitrios A. Prousalis, Ronald Tetzlaff, Spyridon Nikolaidis, Stephan Menzel, Vikas Rana

Proceedings of the 12th International Conference on Modern Circuits and Systems Technologies, 2023

Design and Analysis of Isolated Voltage-Mode Memristor Cellular Nonlinear Network Cells.

Vasileios G. Ntinas, Yongmin Wang, Ahmet Samil Demirkol, Ioannis Messaris, Vikas Rana, Stephan Menzel, Alon Ascoli, Ronald Tetzlaff

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022

Toward Simplified Physics-Based Memristor Modeling of Valence Change Mechanism Devices.

Vasileios G. Ntinas, Alon Ascoli, Ioannis Messaris, Yongmin Wang, Vikas Rana, Stephan Menzel, Ronald Tetzlaff

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Performance Analysis of Memristive-CNN based on a VCM Device Model.

Yongmin Wang, Alon Ascoli, Ronald Tetzlaff, Vikas Rana, Stephan Menzel

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Experimental and Theoretical Analysis of Stateful Logic in Passive and Active Crossbar Arrays for Computation-in-Memory.

Christopher Bengel, Stefan Wiefels, Vikas Rana, Hsin-Yu Chen, Qing-Tai Zhao, Rainer Waser, Henriette Padberg, Fengben Xi, Stephan Menzel

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories.

Felix Staudigl, Hazem Al Indari, Daniel Schön, Dominik Sisejkovic, Farhad Merchant, Jan Moritz Joseph, Vikas Rana, Stephan Menzel, Rainer Leupers

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

NEUROTEC I: Neuro-inspired Artificial Intelligence Technologies for the Electronics of the Future.

Melvin Galicia, Stephan Menzel, Farhad Merchant, Maximilian Müller, Hsin-Yu Chen, Qing-Tai Zhao, Felix Cüppers, Abdur R. Jalil, Qi Shu, Peter Schüffelgen, Gregor Mussler, Carsten Funck, Christian Lanius, Stefan Wiefels, Moritz von Witzleben, Christopher Bengel, Nils Kopperberg, Tobias Ziegler, R. Walied Ahmad, Alexander Krüger, Letícia Maria Bolzani Pöhls, Regina Dittmann, Susanne Hoffmann-Eifert, Vikas Rana, Detlev Grützmacher, Matthias Wuttig, Dirk J. Wouters, Andrei Vescan, Tobias Gemmeke, Joachim Knoch, Max Christian Lemme, Rainer Leupers, Rainer Waser

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

Adaptive Forward Body Bias Voltage Generator.

Vivek Tyagi, Vikas Rana

Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

Negative Voltage Generator and Current DAC Based Regulator For Flash Memory.

Vivek Tyagi, Shivam Kalla, Vikas Rana

Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

Tuning the Memory Window of TaOx ReRAM Using the RF Sputtering Power.

Wonjoo Kim, Dirk J. Wouters, Rainer Waser, Vikas Rana

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Implementation of Multinary Łukasiewicz Logic Using Memristive Devices.

Christopher Bengel, Anne Siemon, Vikas Rana, Stephan Menzel

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

50x Endurance Improvement in TaOx RRAM by Extrinsic Doping.

Tim Kempen, Rainer Waser, Vikas Rana

Proceedings of the IEEE International Memory Workshop, 2021

System Theory Enables a Deep Exploration of ReRAM Cells' Switching Phenomena.

Alon Ascoli, Ronald Tetzlaff, Stephan Menzel, Vikas Rana

Proceedings of the 28th IEEE International Conference on Electronics, 2021

Intelligent patient monitoring for proactive alerting of key personnel in intensive care: A single-center study.

Vikas Rana, Teddy Le Nguyen, Veera Raghava, Prahlad G. Menon

Proceedings of the 43rd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2021

2020

Power Efficient Sense Amplifier For Emerging Non Volatile Memories.

Vivek Tyagi, Vikas Rana, Laura Capecchi, Marcella Carissimi, Marco Pasotti

Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020

Switched Capacitor Based Area Efficient Voltage Quadruple for High Pumping Efficiency.

Vikas Rana, Shivam Kalla

Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020

A 800MHz, O.21pJ, 1.2V to 6V Level Shifter Using Thin Gate Oxide Devices in 65nm LSTP.

Prakhar Shukla, Prabhat Singh, Tushar Maheshwari, Anuj Grover, Vikas Rana

Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

A Compact Model for the Electroforming Process of Memristive Devices.

Camilla La Torre, Andreas Kindsmüller, Seokki Son, Rainer Waser, Vikas Rana, Stephan Menzel

Proceedings of the European Conference on Circuit Theory and Design, 2020

2019

Current DAC Based -40dB PSRR Configurable Output LDO in BCD Technology.

Vivek Tyagi, Vikas Rana, Laura Capecchi, Marcella Carissimi, Riccardo Zurla, Marco Pasotti

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

2-Mb Embedded Phase Change Memory With 16-ns Read Access Time and 5-Mb/s Write Throughput in 90-nm BCD Technology for Automotive Applications.

Marcella Carissimi, Ritesh Mukherjee, Vivek Tyagi, Fabio Disegni, Davide Manfrè, Cesare Torti, Daniele Gallinari, Sandro Rossi, Andrea Gambero, Donatella Brambilla, Paola Zuliani, Riccardo Zurla, Alessandro Cabrini, Guido Torelli, Marco Pasotti, Chantal Auricchio, Emanuela Calvetti, Laura Capecchi, Luigi Croce, Stefano Zanchi, Vikas Rana, Preeti Mishra

Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

2018

Stress Relaxed Multiple Output High-Voltage Level Shifter.

Vikas Rana, Rohan Sinha

IEEE Trans. Circuits Syst. II Express Briefs, 2018

Row decoder for embedded Phase Change Memory using low voltage transistors.

Vikas Rana, Marco Pasotti, Marcella Carissimi

Microelectron. J., 2018

A 32-KB ePCM for Real-Time Data Processing in Automotive and Smart Power Applications.

Marco Pasotti, Riccardo Zurla, Marcella Carissimi, Chantal Auricchio, Donatella Brambilla, Emanuela Calvetti, Laura Capecchi, Luigi Croce, Daniele Gallinari, Cristina Mazzaglia, Vikas Rana, Alessandro Cabrini, Guido Torelli

IEEE J. Solid State Circuits, 2018

CMOS Oscillator Having Stable Frequency with Process, Temperature and Voltage Variation.

Vikas Rana

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Area Efficient NMOS Based Positive and Negative Voltage Multiplier.

Vikas Rana

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Switched Capacitor based High Positive and Negative Voltage Charge-pump using Sample and Hold technique.

Vikas Rana, Abhishek Mittal

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

Switched Capacitor based Area Efficient Positive and Negative Voltage Multiplier.

Vikas Rana

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017

Single charge-pump generating high positive and negative voltages driving common load.

Vikas Rana, Marco Pasotti, F. Desantis

Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

A 10 MHz, 42 ppm/ °C, 69 μW PVT Compensated Latch Based Oscillator in BCD9S Technology for PCM.

Vivek Tyagi, Mohammad S. Hashmi, Ganesh Raj, Vikas Rana

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

A 10 MHz, 73 ppm/°C, 84 µW PVT Compensated Ring Oscillator.

Vivek Tyagi, Mohammad S. Hashmi, Ganesh Raj, Vikas Rana

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

A 32KB 18ns random access time embedded PCM with enhanced program throughput for automotive and smart power applications.

Marco Pasotti, Marcella Carissimi, Chantal Auricchio, Donatella Brambilla, Emanuela Calvetti, Laura Capecchi, Luigi Croce, Daniele Gallinari, Cristina Mazzaglia, Vikas Rana, Riccardo Zurla, Alessandro Cabrini, Guido Torelli

Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

2016

-1.1V to +1.1V 3: 1 Power Switch Architecture for Controlling Body Bias of SRAM Array in 28nm UTBB CMOS FDSOI.

Amit Chhabra, Vikas Rana

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Lowering forming voltage and forming-free behavior of Ta2O5 ReRAM devices.

Wonjoo Kim, Dirk J. Wouters, Stephan Menzel, Christian Rodenbucher, Rainer Waser, Vikas Rana

Proceedings of the 46th European Solid-State Device Research Conference, 2016

2012

Recent progress in redox-based resistive switching.

Rainer Waser, Stephan Menzel, Vikas Rana

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012