Vijaypal Singh Rathor
Orcid: 0000-0002-0326-3282
According to our database1,
Vijaypal Singh Rathor
authored at least 19 papers
between 2017 and 2025.
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Collaborative distances:
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Bibliography
2025
An ensemble learning model for hardware Trojan detection in integrated circuit design.
Comput. Electr. Eng., 2025
Comput. Electr. Eng., 2025
2024
IEEE Trans. Very Large Scale Integr. Syst., February, 2024
SubLock: Sub-Circuit Replacement based Input Dependent Key-based Logic Locking for Robust IP Protection.
CoRR, 2024
2023
Hybrid technique for crop image compression using discrete wavelet transform and sparse singular vector reconstruction.
Comput. Electron. Agric., December, 2023
Multi-Objective Optimization Based Test Pattern Generation for Hardware Trojan Detection.
J. Electron. Test., June, 2023
Int. J. Mach. Learn. Cybern., March, 2023
Microprocess. Microsystems, 2023
2022
Multim. Tools Appl., 2022
Significance driven inverse distance weighted filter to restore impulsive noise corrupted X-ray image.
J. Ambient Intell. Humaniz. Comput., 2022
Cooperative Geometric Scheme for Passive Localization of Target in an Indoor Environment.
Proceedings of the IEEE Symposium Series on Computational Intelligence, 2022
2021
A Lightweight Robust Logic Locking Technique to Thwart Sensitization and Cone-Based Attacks.
IEEE Trans. Emerg. Top. Comput., 2021
Integr., 2021
Int. J. Ad Hoc Ubiquitous Comput., 2021
2020
IEEE Trans. Emerg. Top. Comput., 2020
New lightweight Anti-SAT block design and obfuscation technique to thwart removal attack.
Integr., 2020
2018
New Lightweight Architectures for Secure FSM Design to Thwart Fault Injection and Trojan Attacks.
J. Electron. Test., 2018
An Energy-Efficient Trusted FSM Design Technique to Thwart Fault Injection and Trojan Attacks.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
2017
New Light Weight Threshold Voltage Defined Camouflaged Gates for Trustworthy Designs.
J. Electron. Test., 2017