Vijayaramalingam Periasamy

According to our database1, Vijayaramalingam Periasamy authored at least 4 papers between 2010 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Other 

Links

On csauthors.net:

Bibliography

2016
A 2.7 mW/Channel 48-1000 MHz Direct Sampling Full-Band Cable Receiver.
IEEE J. Solid State Circuits, 2016


2015

2010
A 25 MHz Bandwidth 5th-Order Continuous-Time Low-Pass Sigma-Delta Modulator With 67.7 dB SNDR Using Time-Domain Quantization and Feedback.
IEEE J. Solid State Circuits, 2010


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