Vijay Sheshadri

According to our database, Vijay Sheshadri authored at least 4 papers between 2012 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

Power-Aware Optimization of SoC Test Schedules Using Voltage and Frequency Scaling.

Vijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal

J. Electron. Test., 2017

2013

Optimum Test Schedule for SoC with Specified Clock Frequencies and Supply Voltages.

Vijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Power-aware SoC test optimization through dynamic voltage and frequency scaling.

Vijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

2012

Optimal power-constrained SoC test schedules with customizable clock rates.

Vijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal

Proceedings of the IEEE 25th International SOC Conference, 2012