Vijay Savani

According to our database, Vijay Savani authored at least 3 papers between 2015 and 2024.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of six.

2024

Design and Analysis of Low-Voltage and Low-Power 19T FinFET-TGDI-Based Hybrid Full Adders.

Parthiv Bhau, Vijay Savani

J. Circuits Syst. Comput., January, 2024

2018

Design and analysis of low-power high-speed shared charge reset technique based dynamic latch comparator.

Vijay Savani, N. M. Devashrayee

Microelectron. J., 2018

2015

Analysis & characterization of dual tail current based dynamic latch comparator with modified SR latch using 90nm technology.

Vijay Savani, N. M. Devashrayee

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015