Vijay Kumar Sharma

This page is a disambiguation page, it actually contains mutiple papers from persons of the same or a similar name.

Bibliography

2024
Strengthening wavelet based image steganography using Rubik's cube segmentation and secret image scrambling.
Multim. Tools Appl., October, 2024

FinFET-Based Low-Power Improved PDP 4:2 Approximate Compressor Design.
J. Circuits Syst. Comput., September, 2024

Correction to: W-VDSR: wavelet-based secure image transmission using machine learning VDSR neural network.
Multim. Tools Appl., August, 2024

Improved Stability for Robust and Low-Power SRAM Cell Using FinFET Technology.
J. Circuits Syst. Comput., April, 2024

Exploring Web-Based Translation Resources Applied to Hindi-English Cross-Lingual Information Retrieval.
ACM Trans. Asian Low Resour. Lang. Inf. Process., January, 2024

Enablers Driving Success of Artificial Intelligence in Business Performance: A TISM-MICMAC Approach.
IEEE Trans. Engineering Management, 2024

Creating an immersive environment of Metaverse for businesses.
Australas. J. Inf. Syst., 2024

2023
Identification of Best Image Scrambling and Descrambling Method for Image Steganography.
Multim. Tools Appl., December, 2023

W-VDSR: wavelet-based secure image transmission using machine learning VDSR neural network.
Multim. Tools Appl., November, 2023

Parity generators in QCA nanotechnology for nanocommunication systems.
Nano Commun. Networks, June, 2023

Semantic morphological variant selection and translation disambiguation for cross-lingual information retrieval.
Multim. Tools Appl., March, 2023

Parity Generators for Nanocommunication Systems Using QCA Nanotechnology.
Period. Polytech. Electr. Eng. Comput. Sci., 2023

2022
An efficient low power method for FinFET domino OR logic circuit.
Microprocess. Microsystems, November, 2022

Hilbert quantum image scrambling and graph signal processing-based image steganography.
Multim. Tools Appl., 2022

CNTFET Circuit-Based Wide Fan-In Domino Logic for Low Power Applications.
J. Circuits Syst. Comput., 2022

2021
Design and Simulation for NBTI Aware Logic Gates.
Wirel. Pers. Commun., 2021

A Novel Low Power Technique for FinFET Domino OR Logic.
J. Circuits Syst. Comput., 2021

Multioperative reversible gate design with implementation of 1-bit full adder and subtractor along with energy dissipation analysis.
Int. J. Circuit Theory Appl., 2021

2020
A daubechies DWT based image steganography using smoothing operation.
Int. Arab J. Inf. Technol., 2020

2019
Refined stop-words and morphological variants solutions applied to Hindi-English cross-lingual information retrieval.
J. Intell. Fuzzy Syst., 2019

Visual object tracking based on discriminant DCT features.
Digit. Signal Process., 2019

Designing of Standard Cell Library for GBONOR Approach.
Proceedings of the 2019 International Conference on Advanced Computing and Applications, 2019

2018
Efficient image steganography using graph signal processing.
IET Image Process., 2018

Visual object tracking based on sequential learning of SVM parameter.
Digit. Signal Process., 2018

An Improvement in Statistical Machine Translation in Perspective of Hindi-English Cross-Lingual Information Retrieval.
Computación y Sistemas, 2018

2017
MIL based visual object tracking with kernel and scale adaptation.
Signal Process. Image Commun., 2017

Design of Low Leakage PVT Variations Aware CMOS Bootstrapped Driver Circuit.
J. Circuits Syst. Comput., 2017

Named Entity Identification Based Translation Disambiguation Model.
Proceedings of the Pattern Recognition and Machine Intelligence, 2017

2016
Design of Low Leakage Variability Aware ONOFIC CMOS Standard Cell Library.
J. Circuits Syst. Comput., 2016

Iterative and Fully Pipelined High Throughput Efficient Architectures of AES in FPGA and ASIC.
J. Circuits Syst. Comput., 2016

Exploring Bilingual Word Vectors for Hindi-English Cross-Language Information Retrieval.
Proceedings of the International Conference on Informatics and Analytics, 2016

2014
High Performance Process Variations Aware Technique for Sub-threshold 8T-SRAM Cell.
Wirel. Pers. Commun., 2014

PVT variations aware low leakage INDEP approach for nanoscale CMOS circuits.
Microelectron. Reliab., 2014

Process, Voltage and Temperature Variations Aware Low Leakage Approach for Nanoscale CMOS Circuits.
J. Low Power Electron., 2014

Techniques for Low Leakage nanoscale VLSI Circuits: a Comparative Study.
J. Circuits Syst. Comput., 2014

Non-Recursive Computation of 8 × 8 2D DCT for High accuracy and low Area.
J. Circuits Syst. Comput., 2014

2013
Sentiment classification of review documents using phrase patterns.
Proceedings of the International Conference on Advances in Computing, 2013

2012
A new approach for high performance and efficient design of CORDIC processor.
Proceedings of the 1st International Conference on Recent Advances in Information Technology, 2012

2011
An ASIP for image enhancement applications in spatial domain using LISA.
Proceedings of the International Conference on Recent Trends in Information Systems, 2011


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