Vijay Kiran Kalyanam

Orcid: 0000-0002-4310-2846

According to our database1, Vijay Kiran Kalyanam authored at least 9 papers between 2007 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2021
A Proactive System for Voltage-Droop Mitigation in a 7-nm Hexagon™ Processor.
IEEE J. Solid State Circuits, 2021

A Current and Temperature Limiting System in a 7-nm Hexagon™ Compute Digital Signal Processor.
IEEE J. Solid State Circuits, 2021

35.3 Thread-Level Power Management for a Current- and Temperature-Limiting System in a 7nm Hexagon™ Processor.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020
A Proactive Voltage-Droop-Mitigation System in a 7nm Hexagon™ Processor.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

Functional Test Sequences for Inducing Voltage Droops in a Multi-Threaded Processor.
Proceedings of the IEEE International Test Conference, 2020

Randomized Pulse-Modulating Instruction-Issue Control Circuit for a Current and Temperature Limiting System in a 7nm Hexagon™ Compute DSP.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2017
Power prediction of embedded scalar and vector processor: Challenges and solutions.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

2015
Power-aware multi-voltage custom memory models for enhancing RTL and low power verification.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

2007
Estimating path delay distribution considering coupling noise.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007


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