Vijay Durairaj
According to our database1,
Vijay Durairaj
authored at least 7 papers
between 2003 and 2015.
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Bibliography
2015
Efficient Transistor-Level Symbolic Timing Simulation Using Cached Partial Circuit States.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
2006
Guiding CNF-SAT Search by Analyzing Constraint-Variable Dependencies and Clause Lengths.
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006
2005
Variable Ordering for Efficient SAT Search by Analyzing Constraint-Variable Dependencies.
Proceedings of the Theory and Applications of Satisfiability Testing, 2005
2004
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004
2003
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003