Vijay Dhanasekaran
According to our database1,
Vijay Dhanasekaran
authored at least 8 papers
between 2007 and 2011.
Collaborative distances:
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Bibliography
2011
A 0.8 ps DNL Time-to-Digital Converter With 250 MHz Event Rate in 65 nm CMOS for Time-Mode-Based Sigma Delta Modulator.
IEEE J. Solid State Circuits, 2011
A Continuous Time Multi-Bit Delta Sigma ADC Using Time Domain Quantizer and Feedback Element.
IEEE J. Solid State Circuits, 2011
2009
Design of Three-Stage Class-AB 16ΩHeadphone Driver Capable of Handling Wide Range of Load Capacitance.
IEEE J. Solid State Circuits, 2009
A 20MHz BW 68dB DR CT ΔΣ ADC based on a multi-bit time-domain quantizer and feedback element.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2008
A 1.2mW 1.6Vpp-Swing Class-AB 16Ω Headphone Driver Capable of Handling Load Capacitance up to 22nF.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
Low-Power Architecture and Circuit Techniques for High-Boost Wide-Band G<sub>m</sub>-C Filters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
IEEE J. Solid State Circuits, 2007