Vighnesh Iyer

Orcid: 0000-0001-6934-6577

According to our database1, Vighnesh Iyer authored at least 8 papers between 2019 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2024
RTL-Repair: Fast Symbolic Repair of Hardware Design Code.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023
Simulator Independent Coverage for RTL Hardware Languages.
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2022
A Review of Emotion Detection Systems.
Proceedings of the 5th International Conference on Contemporary Computing and Informatics, 2022

2021
Pattern Census: A Characterization of Pattern Usage in Early Programming Courses.
Proceedings of the SIGCSE '21: The 52nd ACM Technical Symposium on Computer Science Education, 2021

Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI.
IEEE Trans. Very Large Scale Integr. Syst., 2020

2019
Gemmini: An Agile Systolic Array Generator Enabling Systematic Evaluations of Deep-Learning Architectures.
CoRR, 2019

RTL bug localization through LTL specification mining (WIP).
Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design, 2019


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