Victor Navarro-Botello

According to our database, Victor Navarro-Botello authored at least 5 papers between 2006 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2014

Analysis and optimization of dynamically reconfigurable regenerative comparators for ultra-low power 6-bit TC-ADCs in 90 nm CMOS technologies.

Juan A. Montiel-Nelson, Victor Navarro-Botello, Javier Sosa, Tomás Bautista

Microelectron. J., 2014

2009

A geometric approach to register transfer level satisfiability.

Héctor Navarro, Saeid Nooshabadi, Juan A. Montiel-Nelson, Victor Navarro-Botello, Javier Sosa, José C. García

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2007

Analysis of High-Performance Fast Feedthrough Logic Families in CMOS.

Victor Navarro-Botello, Juan A. Montiel-Nelson, Saeid Nooshabadi

IEEE Trans. Circuits Syst. II Express Briefs, 2007

High performance low power CMOS dynamic logic for arithmetic circuits.

Victor Navarro-Botello, Juan A. Montiel-Nelson, Saeid Nooshabadi

Microelectron. J., 2007

2006

Low Power and High Performance Arithmetic Circuits in Feedthrough CMOS Logic Family for Low Power Applications.

Victor Navarro-Botello, Juan A. Montiel-Nelson, Saeid Nooshabadi

J. Low Power Electron., 2006