Victor Moroz
Orcid: 0000-0002-5030-5457
According to our database1,
Victor Moroz
authored at least 12 papers
between 1998 and 2024.
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Bibliography
2024
3DIC System-Technology Co-Optimization with a Focus on the Interplay of Thermal, Power, Timing, and Stress Effects.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
2023
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Proceedings of the 2023 International Symposium on Physical Design, 2023
2018
2016
Transistor design for 5nm and beyond: Slowing down electrons to speed up transistors.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
Proceedings of the 2016 on International Symposium on Physical Design, 2016
A CMOS-compatible boosted transistor having >2× drive current and low leakage current.
Proceedings of the 46th European Solid-State Device Research Conference, 2016
2010
IEEE Des. Test Comput., 2010
2009
Analysis of performance and reliability trade-off in dummy pattern design for 32-nm technology.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
1998
A Hybrid Mesh Generation Method for Two and Three Dimensional Simulation of Semiconductor Processes and Devices.
Proceedings of the 7th International Meshing Roundtable, 1998