Victor Lomné

According to our database1, Victor Lomné authored at least 25 papers between 2008 and 2021.

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Bibliography

2021
A Side Journey to Titan.
IACR Cryptol. ePrint Arch., 2021

A Side Journey To Titan.
Proceedings of the 30th USENIX Security Symposium, 2021

2019
Side-channel Attacks on Blinded Scalar Multiplications Revisited.
IACR Cryptol. ePrint Arch., 2019

2017
An Industrial Outlook on Challenges of Hardware Security in Digital Economy - Extended Abstract -.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2017

2016
Cost-Effective Design Strategies for Securing Embedded Processors.
IEEE Trans. Emerg. Top. Comput., 2016

Practical Fault Attacks on Authenticated Encryption Modes for AES.
IACR Cryptol. ePrint Arch., 2016

Statistical Fault Attacks on Nonce-Based Authenticated Encryption Schemes.
Proceedings of the Advances in Cryptology - ASIACRYPT 2016, 2016

2014
Practical improvements of side-channel attacks on AES: feedback from the 2nd DPA contest.
J. Cryptogr. Eng., 2014

How to Estimate the Success Rate of Higher-Order Side-Channel Attacks.
IACR Cryptol. ePrint Arch., 2014

Side-Channel Attack against RSA Key Generation Algorithms.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2014, 2014

2013
Behind the Scene of Side Channel Attacks.
IACR Cryptol. ePrint Arch., 2013

Implementing Lightweight Block Ciphers on x86 Architectures.
IACR Cryptol. ePrint Arch., 2013

Fault Attacks on AES with Faulty Ciphertexts Only.
Proceedings of the 2013 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2013

Collision-Correlation Attack against Some 1st-Order Boolean Masking Schemes in the Context of Secure Devices.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2013

2012
Enhancing Electromagnetic Analysis Using Magnitude Squared Incoherence.
IEEE Trans. Very Large Scale Integr. Syst., 2012

On the Need of Randomness in Fault Attack Countermeasures - Application to AES.
Proceedings of the 2012 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2012

2011
Formal Framework for the Evaluation of Waveform Resynchronization Algorithms.
Proceedings of the Information Security Theory and Practice. Security and Privacy of Mobile Devices in Wireless Communication, 2011

Combined Fault and Side-Channel Attack on Protected Implementations of AES.
Proceedings of the Smart Card Research and Advanced Applications, 2011

2010
A GALS pipeline DES architecture to increase robustness against DPA and DEMA attacks.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

Modeling Time Domain Magnetic Emissions of ICs.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010

Differential Power Analysis enhancement with statistical preprocessing.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Enhancing Electromagnetic Attacks Using Spectral Coherence Based Cartography.
Proceedings of the VLSI-SoC: Technologies for Systems Integration, 2009

Evaluation on FPGA of triple rail logic robustness against DPA and DEMA.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Evaluating the robustness of secure triple track logic through prototyping.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

Triple Rail Logic Robustness against DPA.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008


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