Vicente Torres

Orcid: 0000-0002-6829-7889

Affiliations:
  • Technical University of Valencia, Spain


According to our database1, Vicente Torres authored at least 20 papers between 2002 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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Bibliography

2019
A Test Vector Generation Method Based on Symbol Error Probabilities for Low-Complexity Chase Soft-Decision Reed-Solomon Decoding.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Reed-Solomon Decoder Based on a Modified ePIBMA for Low-Latency 100 Gbps Communication Systems.
Circuits Syst. Signal Process., 2019

2018
Soft-decision LCC Decoder Architecture with n=4 for RS(255, 239).
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

High-Throughput One-Channel RS(255, 239) Decoder.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

2017
A Fast and Low-Complexity Operator for the Computation of the Arctangent of a Complex Number.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Fast- and Low-Complexity atan2(a, b) Approximation [Tips and Tricks].
IEEE Signal Process. Mag., 2017

2014
Reduced-Complexity Min-Sum Algorithm for Decoding LDPC Codes With Low Error-Floor.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

2012
Hardware Architecture of a Gaussian Noise Generator Based on the Inversion Method.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

Fully-parallel LUT-based (2048, 1723) LDPC code decoder for FPGA.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

High-throughput FPGA-based emulator for structured LDPC codes.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2010
FPGA-implementation of atan(Y/X) based on logarithmic transformation and LUT-based techniques.
J. Syst. Archit., 2010

2009
Design and FPGA-Implementation of a High Performance Timing Recovery Loop for Broadband Communications.
J. Signal Process. Syst., 2009

Design of Power and Area Efficient Digital Down-converters for Broadband Communications Systems.
J. Signal Process. Syst., 2009

2007
Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs.
J. VLSI Signal Process., 2007

FFT Spectrum Analyzer Project for Teaching Digital Signal Processing With FPGA Devices.
IEEE Trans. Educ., 2007

Design of an efficient digital down-converter for a SDR-based DVB-S receiver.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006
The use of CORDIC in software defined radios: a tutorial.
IEEE Commun. Mag., 2006

Design of high performance timing recovery loops for communication applications.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

2003
DIGIMOD: A Tool to Implement FPGA-Based Digital IF and Baseband Modems.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

2002
Efficient FPGA-based QPSK Demodulation Loops: Application to the DVB Standard.
Proceedings of the Field-Programmable Logic and Applications, 2002


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