Venkatram Krishnaswamy

According to our database, Venkatram Krishnaswamy authored at least 19 papers between 1995 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2016

SPARC M7: A 20 nm 32-Core 64 MB L3 Cache Processor.

Georgios K. Konstadinidis, Hongping Penny Li, Francis Schumacher, Venkatram Krishnaswamy, Hoyeol Cho, Sudesna Dash, Robert P. Masleid, Chaoyang Zheng, Yuanjung David Lin, Paul Loewenstein, Heechoul Park, Vijay Srinivasan, Dawei Huang, Changku Hwang, Wenjay Hsu, Curtis McAllister, Jeffrey Brooks, Ha Pham, Sebastian Turullols, Yifan YangGong, Robert T. Golla, Alan P. Smith, Ali Vahidsafa

IEEE J. Solid State Circuits, 2016

2015

4.2 A 20nm 32-Core 64MB L3 cache SPARC M7 processor.

Penny Li, Jinuk Luke Shin, Georgios K. Konstadinidis, Francis Schumacher, Venkatram Krishnaswamy, Hoyeol Cho, Sudesna Dash, Robert P. Masleid, Chaoyang Zheng, Yuanjung David Lin, Paul Loewenstein, Heechoul Park, Vijay Srinivasan, Dawei Huang, Changku Hwang, Wenjay Hsu, Curtis McAllister

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

4.3 Fine-grained adaptive power management of the SPARC M7 processor.

Venkatram Krishnaswamy, Jeffrey Brooks, Georgios K. Konstadinidis, Curtis McAllister, Ha Pham, Sebastian Turullols, Jinuk Luke Shin, Yifan YangGong, Haowei Zhang

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014

A 3.6 GHz 16-Core SPARC SoC Processor in 28 nm.

Jason Hart, Hoyeol Cho, Yuefei Ge, Gregory Gruber, Dawei Huang, Changku Hwang, Daisy Jian, Timothy Johnson, Georgios K. Konstadinidis, Venkatram Krishnaswamy, Lance Kwong, Robert P. Masleid, Rakesh Mehta, Umesh Nawathe, Aparna Ramachandran, Harikaran Sathianathan, Yongning Sheng, Jinuk Luke Shin, Sebastian Turullols, Zuxu Qin, King C. Yen

IEEE J. Solid State Circuits, 2014

Asymmetric Frequency Locked Loop (AFLL) for adaptive clock generation in a 28nm SPARC M6 processor.

Yifan YangGong, Sebastian Turullols, Daniel Woo, Changku Huang, King C. Yen, Venkatram Krishnaswamy, Kalon Holdbrook, Jinuk Luke Shin

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013

Bandwidth and power management of glueless 8-socket SPARC T5 system.

Venkatram Krishnaswamy, Dawei Huang, Sebastian Turullols, Jinuk Luke Shin

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2002

Automatic Parallelization of Compiled Event Driven VHDL Simulation.

Venkatram Krishnaswamy, Gagan Hasteer, Prithviraj Banerjee

IEEE Trans. Computers, 2002

2001

A study of bridging defect probabilities on a Pentium (TM) 4 CPU.

Venkatram Krishnaswamy, A. B. Ma, Praveen Vishakantaiah

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

2000

A switch level fault simulation environment.

Venkatram Krishnaswamy, Jeremy Casas, Thomas Tetzlaff

Proceedings of the 37th Conference on Design Automation, 2000

1998

Parallel Compiled Event Driven VHDL Simulation.

Venkatram Krishnaswamy, Prithviraj Banerjee

Proceedings of the 12th international conference on Supercomputing, 1998

WADE: a Web-based automated parallel CAD environment.

Dhruva R. Chakrabarti, Pramod G. Joisha, John A. Chandy, Krishnaswamy Krishnaswamy, Venkatram Krishnaswamy, Prithviraj Banerjee

Proceedings of the 5th International Conference On High Performance Computing, 1998

1997

Parallel Algorithms for VHDL Simulation

Venkatram Krishnaswamy

PhD thesis, 1997

Implications of VHDL timing models on simulation and software synthesis.

Venkatram Krishnaswamy, Rajesh Gupta, Prithviraj Banerjee

J. Syst. Archit., 1997

Performance Evaluation of Message-Driven Parallel VLSI CAD Applications on General Purpose Multiprocessors.

John G. Holm, John A. Chandy, Steven Parkes, Sumit Roy, Venkatram Krishnaswamy, Gagan Hasteer, Prithviraj Banerjee

Proceedings of the 11th international conference on Supercomputing, 1997

Load Balancing and Workload Minimization Of Overlapping Parallel Tasks.

Venkatram Krishnaswamy, Gagan Hasteer, Prithviraj Banerjee

Proceedings of the 1997 International Conference on Parallel Processing (ICPP '97), 1997

A procedure for software synthesis from VHDL models.

Venkatram Krishnaswamy, Rajesh Gupta, Prithviraj Banerjee

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996

Actor Based Parallel VHDL Simulation Using Time Warp.

Venkatram Krishnaswamy, Prithviraj Banerjee

Proceedings of the Tenth Workshop on Parallel and Distributed Simulation, 1996

1995

System Modeling, Performance Analysis, and Evolutionary Prototyping with Hardware Description Languages.

Sidharta Mohanty, Venkatram Krishnaswamy, Philip A. Wilsey

Proceedings of the MASCOTS '95, 1995

graze: A Tool for Performance Visualization and Analysis.

Lantz Moore, Debra A. Hensgen, David Charley, Venkatram Krishnaswamy, Dale E. Martin, Timothy J. McBrayer, Philip A. Wilsey

Proceedings of the 1995 International Conference on Parallel Processing, 1995