Venkataraman Mahalingam

According to our database, Venkataraman Mahalingam authored at least 15 papers between 2003 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2012

Dynamic clock stretching for variation compensation in VLSI circuit design.

Venkataraman Mahalingam, Nagarajan Ranganathan, Ransford Hyman Jr.

ACM J. Emerg. Technol. Comput. Syst., 2012

2010

Timing-Based Placement Considering Uncertainty Due to Process Variations.

Venkataraman Mahalingam, N. Ranganathan

IEEE Trans. Very Large Scale Integr. Syst., 2010

A VLSI Architecture and Algorithm for Lucas-Kanade-Based Optical Flow Computation.

Venkataraman Mahalingam, Koustav Bhattacharya, N. Ranganathan, Hari Chakravarthula, Robin R. Murphy, Kevin S. Pratt

IEEE Trans. Very Large Scale Integr. Syst., 2010

2009

Variation-aware multimetric optimization during gate sizing.

Nagarajan Ranganathan, Upavan Gupta, Venkataraman Mahalingam

ACM Trans. Design Autom. Electr. Syst., 2009

A VLSI System Architecture for Optical Flow Computation.

Koustav Bhattacharya, Venkataraman Mahalingam, Nagarajan Ranganathan

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008

A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing.

Venkataraman Mahalingam, N. Ranganathan, J. E. Harlow

IEEE Trans. Very Large Scale Integr. Syst., 2008

A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing.

Venkataraman Mahalingam, Nagarajan Ranganathan

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Simultaneous optimization of total power, crosstalk noise, and delay under uncertainty.

N. Ranganathan, Upavan Gupta, Venkataraman Mahalingam

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2007

Variation Aware Timing Based Placement Using Fuzzy Programming.

Venkataraman Mahalingam, N. Ranganathan

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

2006

Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition.

Venkataraman Mahalingam, Nagarajan Ranganathan

IEEE Trans. Computers, 2006

An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition.

Venkataraman Mahalingam, N. Ranganathan

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

A novel approach for variation aware power minimization during gate sizing.

Venkataraman Mahalingam, N. Ranganathan, Justin E. Harlow III

Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

2005

A Nonlinear Programming Based Power Optimization Methodology for Gate Sizing and Voltage Selection.

Venkataraman Mahalingam, N. Ranganathan

Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

2004

Crosstalk Fault Tolerant Processor Architecture - A Power Aware Design.

N. Venkateswaran, V. Barath Kumar, R. Raghavan, R. Srinivas, S. Subramanian, V. Balaji, Venkataraman Mahalingam, T. L. Rajaprabhu

Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

2003

Analysis of Bit Transition Count for EDAC Encoded FSM.

N. Venkateswaran, V. Balaji, Venkataraman Mahalingam, T. L. Rajaprabhu

Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003