Venkata Reddy Kolagatla

According to our database, Venkata Reddy Kolagatla authored at least 4 papers between 2021 and 2024.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of six.

2024

A Novel and Efficient SPI enabled RSA Crypto Accelerator for Real-Time applications.

Venkata Reddy Kolagatla, Aneesh Raveendran, Vivian Desalphine

Proceedings of the 28th International Symposium on VLSI Design and Test, 2024

Enhancing Performance and Scalability: A Novel Hardware Architecture for 1024-bit Miller-Rabin Primality Testing.

Venkata Reddy Kolagatla, Aneesh Raveendran, Vivian Desalphine

Proceedings of the 28th International Symposium on VLSI Design and Test, 2024

2021

A Randomized Montgomery Powering Ladder Exponentiation for Side-Channel Attack Resilient RSA and Leakage Assessment.

Venkata Reddy Kolagatla, J. Mervin, Shabbir Darbar, David Selvakumar, Sankha Saha

Proceedings of the 25th International Symposium on VLSI Design and Test, 2021

Area-Time Scalable High Radix Montgomery Modular Multiplier for Large Modulus.

Venkata Reddy Kolagatla, Vivian Desalphine, David Selvakumar

Proceedings of the 25th International Symposium on VLSI Design and Test, 2021