Venkata Naveen Kolakaluri

According to our database1, Venkata Naveen Kolakaluri authored at least 8 papers between 2022 and 2024.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
A 6.25-MHz 3.4-mW Single Clock DPWM Technique Using Matrix Shift Array.
IEEE Trans. Very Large Scale Integr. Syst., May, 2024

A Wide Range 2-to-2048 Division Ratio Frequency Divider Using 40-nm CMOS Process.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

A 10-MHz 5-V On-chip 6-layer Multi-level Digital Transformer Using T18HVG2 Process.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
A 99.6 % Duty Cycle High-Resolution DPWM Using Reconfiguring Decoder.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

SiC MOSFET High Side Gate Driver Design Using HV CMOS Process.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Matrix Phase Shift Based DPWM Technique To Achieve 90% Duty Cycle.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2-Level Miller Detection-Based High Side Gate Driver Design for Power MOSFETs.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023

2022
A Novel Constant-pulse Scheme for Synchronous Half-bridge Converter Module.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022


  Loading...