Veeresh Babu Vulligaddala

According to our database, Veeresh Babu Vulligaddala authored at least 7 papers between 2015 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2020

A 7-Cell, Stackable, Li-Ion Monitoring and Active/Passive Balancing IC With In-Built Cell Balancing Switches for Electric and Hybrid Vehicles.

Veeresh Babu Vulligaddala, Sandeep Vernekar, Sudhakar Singamala, Ravi Kumar Adusumalli, Vijay Ele, Manfred Brandl, M. B. Srinivas

IEEE Trans. Ind. Informatics, 2020

Regression Based Mixed Signal Verification of an Ambient Light Sensor Interface.

R. Deepak, S. J. Parvathy, S. Arya, Veeresh Babu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2018

A Digitally Calibrated Bandgap Reference With 0.06% Error for Low-Side Current Sensing Application.

Veeresh Babu Vulligaddala, Ravikumar Adusumalli, Sudhakar Singamala, M. B. Srinivas

IEEE J. Solid State Circuits, 2018

2017

A Switched-Capacitor Amplifier with True Rail-to-Rail Input Range without Using a Rail-to-Rail Op-Amp.

Anjali Gopinath, Ravi Kumar Adusumalli, Veeresh Babu Vulligaddala, M. B. Srinivas

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

CMOS mixed signal SoC for low-side current sensing.

Rahul Thottathil, Veeresh Babu Vulligaddala, Bibhudatta Sahoo

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016

Bootstrapped leakage suppression switch for switched capacitor circuits with zero input common mode.

T. Rahul, Bibhu Datta Sahoo, Veeresh Babu Vulligaddala, Chandra Nyshadham

Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

2015

A Wide Dynamic-Range Low-Power Signal Conditioning Circuit for Low-Side Current Sensing Application.

T. Rahul, Bibhudatta Sahoo, S. Arya, S. J. Parvathy, Veeresh Babu Vulligaddala

Proceedings of the 28th International Conference on VLSI Design, 2015