Vassos Soteriou

Magnus Själander

Proceedings of the CF '22: 19th ACM International Conference on Computing Frontiers, Turin, Italy, May 17, 2022

2021

Interposer-Based Root of Trust.

[BibT_eX]

[DOI]

CoRR, 2021

2020

2.5D Root of Trust: Secure System-Level Integration of Untrusted Chiplets.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2020

Towards fault adaptive routing in metasurface controller networks.

[BibT_eX]

[DOI]

J. Syst. Archit., 2020

Toward Fault-Tolerant Deadlock-Free Routing in HyperSurface-Embedded Controller Networks.

[BibT_eX]

[DOI]

IEEE Netw. Lett., 2020

Design of a Near-Ideal Fault-Tolerant Routing Algorithm for Network-on-Chip-Based Multicores.

[BibT_eX]

[DOI]

Costas Iordanou

Konstantinos Aisopos

CoRR, 2020

2019

Toward data-driven architectural support in improving the performance of future HPC architectures.

[BibT_eX]

[DOI]

George Matheou

Paraskevas Evripidou

Parallel Comput., 2019

An Interposer-Based Root of Trust: Seize the Opportunity for Secure System-Level Integration of Untrusted Chiplets.

[BibT_eX]

[DOI]

CoRR, 2019

2018

Fault Adaptive Routing in Metasurface Controller Networks.

[BibT_eX]

[DOI]

Proceedings of the 11th International Workshop on Network on Chip Architectures, 2018

2017

Silica-Embedded Silicon Nanophotonic On-Chip Networks.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Minimal exercise vector generation for reliability improvement.

[BibT_eX]

[DOI]

P. Madhukar Reddy

Stavros Hadjitheophanous

Maria K. Michael

Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

2016

A Holistic Approach Towards Intelligent Hotspot Prevention in Network-on-Chip-Based Multicores.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

2015

Use It or Lose It: Proactive, Deterministic Longevity in Future Chip Multiprocessors.

[BibT_eX]

[DOI]

Hyungjun Kim

Siva Bhanu Krishna Boga

Stavros Hadjitheophanous

Maria K. Michael

ACM Trans. Design Autom. Electr. Syst., 2015

Wear-Aware Adaptive Routing for Networks-on-Chips.

[BibT_eX]

[DOI]

Arseni Vitkovski

Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

Designing High-Performance, Power-Efficient NoCs With Embedded Silicon-in-Silica Nanophotonics.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

Clotho: Proactive wearout deceleration in Chip-Multiprocessor interconnects.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Design of high-performance, power-efficient optical NoCs using Silica-embedded silicon nanophotonics.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Towards High-Performance and Power-Efficient Optical NoCs Using Silicon-in-Silica Photonic Components.

[BibT_eX]

[DOI]

Proceedings of the Ninth International Workshop on Interconnection Network Architectures: On-Chip, 2015

2014

Hermes: Architecting a top-performing fault-tolerant routing algorithm for Networks-on-Chips.

[BibT_eX]

[DOI]

Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

Hermes: Architecting a top-performing fault-tolerant routing algorithm for Networks-on-Chips.

[BibT_eX]

[DOI]

Costas Iordanou

Konstantinos Aisopos

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Up by their bootstraps: Online learning in Artificial Neural Networks for CMP uncore power management.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2013

Dynamic fault-tolerant routing algorithm for networks-on-chip based on localised detouring paths.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2013

Use it or lose it: wear-out and lifetime in future chip multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

2012

A Dynamically Adjusting Gracefully Degrading Link-Level Fault-Tolerant Mechanism for NoCs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Intelligent Hotspot Prediction for Network-on-Chip-Based Multicore Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Intelligent On/Off Dynamic Link Management for On-Chip Networks.

[BibT_eX]

[DOI]

Andreas G. Savva

J. Electr. Comput. Eng., 2012

Virtualizing Virtual Channels for Increased Network-on-Chip Robustness and Upgradeability.

[BibT_eX]

[DOI]

Marios Evripidou

Jongman Kim

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

HPRA: A pro-active Hotspot-Preventive high-performance routing algorithm for Networks-on-Chips.

[BibT_eX]

[DOI]

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

A highly robust distributed fault-tolerant routing algorithm for NoCs with localized rerouting.

[BibT_eX]

[DOI]

Proceedings of the 2012 Interconnection Network Architecture, 2012

2011

Extending the Effective Throughput of NoCs With Distributed Shared-Buffer Routers.

[BibT_eX]

[DOI]

Rohit Sunkam Ramanujam

Bill Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Intelligent On/Off Link Management for On-chip Networks.

[BibT_eX]

[DOI]

Andreas G. Savva

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

2010

Design of a High-Throughput Distributed Shared-Buffer NoC Router.

[BibT_eX]

[DOI]

Rohit Sunkam Ramanujam

Bill Lin

Proceedings of the NOCS 2010, 2010

Intelligent NOC Hotspot Prediction.

[BibT_eX]

[DOI]

Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010

An Artificial Neural Network-Based Hotspot Prediction Mechanism for NoCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

A fine-grained link-level fault-tolerant mechanism for networks-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Computer Design, 2010

2009

A High-Throughput Distributed Shared-Buffer NoC Router.

[BibT_eX]

[DOI]

Rohit Sunkam Ramanujam

Bill Lin

IEEE Comput. Archit. Lett., 2009

2007

Polaris: A System-Level Roadmapping Toolchain for On-Chip Interconnection Networks.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

Exploring the Design Space of Self-Regulating Power-Aware On/Off Interconnection Networks.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2007

Software-directed power-aware interconnection networks.

[BibT_eX]

[DOI]

Noel Eisley

ACM Trans. Archit. Code Optim., 2007

2006

A Statistical Traffic Model for On-Chip Interconnection Networks.

[BibT_eX]

[DOI]

Hangsheng Wang

Proceedings of the 14th International Symposium on Modeling, 2006

Polaris: A System-Level Roadmap for On-Chip Interconnection Networks.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

High-level power analysis for multi-core chips.

[BibT_eX]

[DOI]

Noel Eisley

Proceedings of the 2006 International Conference on Compilers, 2006

2004

Design-Space Exploration of Power-Aware On/Off Interconnection Networks.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

2003

Dynamic power management for power optimization of interconnection networks using on/off links.

[BibT_eX]

[DOI]