Vassilis Papaefstathiou

According to our database, Vassilis Papaefstathiou authored at least 55 papers between 2004 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Low-latency Communication in RISC-V Clusters.

Michalis Gianioudis, Pantelis Xirouchakis, Charisios Loukas, Evangelos Mageiropoulos, Orestis Mousouros, Sokratis Mpartzis, Aggelos Ioannou, Vassilis Papaefstathiou, Manolis Katevenis, Nikolaos Chrysos

Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region, 2024

2023

The ExaNeSt Prototype: Evaluation of Efficient HPC Communication Hardware in an ARM-based Multi-FPGA Rack.

Manolis Ploumidis, Fabien Chaix, Nikolaos Chrysos, Marios Asiminakis, Vassilis Flouris, Nikolaos D. Kallimanis, Nikolaos Kossifidis, Michael Nikoloudakis, Polydoros Petrakis, Nikolaos Dimou, Michalis Gianioudis, Georgios Ieronymakis, Aggelos Ioannou, George Kalokerinos, Pantelis Xirouchakis, Georgios Ailamakis, Astrinos Damianakis, Michael Ligerakis, Ioannis Makris, Theocharis Vavouris, Manolis Katevenis, Vassilis Papaefstathiou, Manolis Marazakis, Iakovos Mavroidis

CoRR, 2023

Software Development Vehicles to Enable Extended and Early Co-design: A RISC-V and HPC Case of Study.

Filippo Mantovani, Pablo Vizcaino, Fabio Banchelli, Marta Garcia-Gasulla, Roger Ferrer, Georgios Ieronymakis, Nikolaos Dimou, Vassilis Papaefstathiou, Jesús Labarta

Proceedings of the High Performance Computing, 2023

Short Reasons for Long Vectors in HPC CPUs: A Study Based on RISC-V.

Pablo Vizcaino, Georgios Ieronymakis, Nikolaos Dimou, Vassilis Papaefstathiou, Jesús Labarta, Filippo Mantovani

Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023

eProcessor: European, Extendable, Energy-Efficient, Extreme-Scale, Extensible, Processor Ecosystem.

Lluc Alvarez, Abraham Ruiz, Arnau Bigas-Soldevilla, Pavel Kuroedov, Alberto González, Hamsika Mahale, Noe Bustamante, Albert Aguilera, Francesco Minervini, Javier Salamero, Oscar Palomar, Vassilis Papaefstathiou, Antonis Psathakis, Nikolaos Dimou, Michalis Giaourtas, Iasonas Mastorakis, Georgios Ieronymakis, Georgios-Michail Matzouranis, Vassilis Flouris, Nick Kossifidis, Manolis Marazakis, Bhavishya Goel, Madhavan Manivannan, Ahsen Ejaz, Panagiotis Strikos, Mateo Vázquez, Ioannis Sourdis, Pedro Trancoso, Per Stenström, Jens Hagemeyer, Lennart Tigges, Nils Kucza, Jean-Marc Philippe, Ioannis Papaefstathiou

Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023

2022

Optimized Page Fault Handling During RDMA.

Antonis Psistakis, Nikos Chrysos, Fabien Chaix, Marios Asiminakis, Michalis Gianioudis, Pantelis Xirouchakis, Vassilis Papaefstathiou, Manolis Katevenis

IEEE Trans. Parallel Distributed Syst., 2022

2021

HighwayNoC: Approaching Ideal NoC Performance With Dual Data Rate Routers.

Ahsen Ejaz, Vassilis Papaefstathiou, Ioannis Sourdis

IEEE/ACM Trans. Netw., 2021

Multilevel simulation-based co-design of next generation HPC microprocessors.

Lilia Zaourar, Mohamed Benazouz, Ayoub Mouhagir, Fatma Jebali, Tanguy Sassolas, Jean-Christophe Weill, Carlos Falquez, Nam Ho, Dirk Pleiter, Antoni Portero, Estela Suarez, Polydoros Petrakis, Vassilis Papaefstathiou, Manolis Marazakis, Milan Radulovic, Francesc Martínez, Adrià Armejach, Marc Casas, Alejandro Nocua, Romain Dolbeau

Proceedings of the 2021 International Workshop on Performance Modeling, 2021

2020

UNILOGIC: A Novel Architecture for Highly Parallel Reconfigurable Systems.

Aggelos D. Ioannou, Konstantinos Georgopoulos, Pavlos Malakonakis, Dionisios N. Pnevmatikatos, Vassilis D. Papaefstathiou, Ioannis Papaefstathiou, Iakovos Mavroidis

ACM Trans. Reconfigurable Technol. Syst., 2020

On Architectural Support for Instruction Set Randomization.

George Christou, Giorgos Vasiliadis, Vassilis Papaefstathiou, Antonis Papadogiannakis, Sotiris Ioannidis

ACM Trans. Archit. Code Optim., 2020

Proceedings of the Thirteenth International Workshop on Programmability and Architectures for Heterogeneous Multicores (MULTIPROG-2020).

Miquel Pericàs, Oscar Palomar, Vassilis Papaefstathiou, Mahmoud Eljammaly

CoRR, 2020

Performance and Energy Footprint Assessment of FPGAs and GPUs on HPC Systems Using Astrophysics Application.

David Goz, Georgios Ieronymakis, Vassilis Papaefstathiou, Nikolaos Dimou, Sara Bertocco, Francesco Simula, Antonio Ragagnin, Luca Tornatore, Igor Coretti, Giuliano Taffoni

Comput., 2020

PART: Pinning Avoidance in RDMA Technologies.

Antonis Psistakis, Nikos Chrysos, Fabien Chaix, Marios Asiminakis, Michalis Giannioudis, Pantelis Xirouchakis, Vassilis Papaefstathiou, Manolis Katevenis

Proceedings of the 14th IEEE/ACM International Symposium on Networks-on-Chip, 2020

Hybrid2: Combining Caching and Migration in Hybrid Memory Systems.

Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, Ioannis Sourdis

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

2019

Prototyping a Configurable Cache/Scratchpad Memory with Virtualized User-Level RDMA Capability.

George Kalokerinos, Vassilis Papaefstathiou, George Nikiforos, Stamatis G. Kavadias, Xiaojun Yang, Dionisios N. Pnevmatikatos, Manolis Katevenis

Trans. High Perform. Embed. Archit. Compil., 2019

Decoupled Fused Cache: Fusing a Decoupled LLC with a DRAM Cache.

Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, Ioannis Sourdis

ACM Trans. Archit. Code Optim., 2019

Direct N-body application on low-power and energy-efficient parallel architectures.

David Goz, Giorgos Ieronymakis, Vassilis Papaefstathiou, Nikolaos Dimou, Sara Bertocco, Antonio Ragagnin, Luca Tornatore, Giuliano Taffoni, Igor Coretti

CoRR, 2019

Software and Hardware Co-design for Low-Power HPC Platforms.

Manolis Ploumidis, Nikolaos D. Kallimanis, Marios Asiminakis, Nikos Chrysos, Pantelis Xirouchakis, Michalis Gianoudis, Leandros Tzanakis, Nikolaos Dimou, Antonis Psistakis, Panagiotis Peristerakis, Giorgos Kalokairinos, Vassilis Papaefstathiou, Manolis Katevenis

Proceedings of the High Performance Computing, 2019

Implementation and Impact of an Ultra-Compact Multi-FPGA Board for Large System Prototyping.

Fabien Chaix, Georgios Ailamakis, Theocharis Vavouris, Astrinos Damianakis, Manolis Katevenis, Iakovos Mavroidis, Aggelos Ioannou, Nikolaos Kossifidis, Nikolaos Dimou, Giorgos Ieronymakis, Manolis Marazakis, Vassilis Papaefstathiou, Vassilis Flouris, Mihailis Ligerakis

Proceedings of the 2019 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing, 2019

Direct N-Body Application on Low-Power and Energy-Efficient Parallel Architectures.

Georgios Ieronymakis, Vassilis Papaefstathiou, Nikolaos Dimou, Sara Bertocco, Antonio Ragagnin, Luca Tornatore, Giuliano Taffoni, Igor Coretti

Proceedings of the Parallel Computing: Technology Trends, 2019

LLC-Guided Data Migration in Hybrid Memory Systems.

Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, Ioannis Sourdis

Proceedings of the 2019 IEEE International Parallel and Distributed Processing Symposium, 2019

2018

Global Dead-Block Management for Task-Parallel Programs.

Madhavan Manivannan, Miquel Pericàs, Vassilis Papaefstathiou, Per Stenström

ACM Trans. Archit. Code Optim., 2018

DDRNoC: Dual Data-Rate Network-on-Chip.

Ahsen Ejaz, Vassilios Papaefstathiou, Ioannis Sourdis

ACM Trans. Archit. Code Optim., 2018

FreewayNoC: A DDR NoC with Pipeline Bypassing.

Ahsen Ejaz, Vassilios Papaefstathiou, Ioannis Sourdis

Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

ProFess: A Probabilistic Hybrid Main Memory Management Framework for High Performance and Fairness.

Dmitry Knyaginin, Vassilis Papaefstathiou, Per Stenström

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

FusionCache: Using LLC tags for DRAM cache.

Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, Ioannis Sourdis

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

SLOOP: QoS-Supervised Loop Execution to Reduce Energy on Heterogeneous Architectures.

Muhammad Waqar Azhar, Per Stenström, Vassilis Papaefstathiou

ACM Trans. Archit. Code Optim., 2017

Runtime-Assisted Global Cache Management for Task-Based Parallel Programs.

Madhavan Manivannan, Miquel Pericàs, Vassilis Papaefstathiou, Per Stenström

IEEE Comput. Archit. Lett., 2017

Modeling energy-performance tradeoffs in ARM big.LITTLE architectures.

Evangelos Vasilakis, Ioannis Sourdis, Vassilis Papaefstathiou, Antonis Psathakis, Manolis G. H. Katevenis

Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

Odd-ECC: on-demand DRAM error correcting codes.

Alirad Malek, Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, Ioannis Sourdis

Proceedings of the International Symposium on Memory Systems, 2017

2016

Adaptive Row Addressing for Cost-Efficient Parallel Memory Protocols in Large-Capacity Memories.

Dmitry Knyaginin, Vassilis Papaefstathiou, Per Stenström

Proceedings of the Second International Symposium on Memory Systems, 2016

RADAR: Runtime-assisted dead region management for last-level caches.

Madhavan Manivannan, Vassilis Papaefstathiou, Miquel Pericàs, Per Stenström

Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

ECOSCALE: Reconfigurable computing and runtime system for future exascale systems.

Iakovos Mavroidis, Ioannis Papaefstathiou, Luciano Lavagno, Dimitrios S. Nikolopoulos, Dirk Koch, John Goodacre, Ioannis Sourdis, Vassilis Papaefstathiou, Marcello Coppola, Manuel Palomino

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

A Systematic Evaluation of Emerging Mesh-like CMP NoCs.

Antonis Psathakis, Vassilis Papaefstathiou, Nikolaos Chrysos, Fabien Chaix, Evangelos Vasilakis, Dionisios N. Pnevmatikatos, Manolis Katevenis

Proceedings of the Eleventh ACM/IEEE Symposium on Architectures for networking and communications systems, 2015

2014

Architectural support for software-guided energy reduction of manycore communication

Vassilis Papaefstathiou

PhD thesis, 2014

FPGA prototyping of emerging manycore architectures for parallel programming research using Formic boards.

Spyros Lyberis, George Kalokerinos, Michalis Lygerakis, Vassilis Papaefstathiou, Iakovos Mavroidis, Manolis Katevenis, Dionisios N. Pnevmatikatos, Dimitrios S. Nikolopoulos

J. Syst. Archit., 2014

Design space exploration for fair resource-allocated NoC architectures.

Antonis Psathakis, Vassilis Papaefstathiou, Manolis Katevenis, Dionisios N. Pnevmatikatos

Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

Design trade-offs in energy efficient NoC architectures.

Antonis Psathakis, Vassilis Papaefstathiou, Manolis Katevenis, Dionisios N. Pnevmatikatos

Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

2013

NP-SARC: Scalable network processing in the SARC multi-core FPGA platform.

Christoforos Kachris, George Nikiforos, Vassilis Papaefstathiou, Stamatis G. Kavadias, Manolis Katevenis

J. Syst. Archit., 2013

Prefetching and cache management using task lifetimes.

Vassilis Papaefstathiou, Manolis Katevenis, Dimitrios S. Nikolopoulos, Dionisios N. Pnevmatikatos

Proceedings of the International Conference on Supercomputing, 2013

ASIST: architectural support for instruction set randomization.

Antonis Papadogiannakis, Laertis Loutsis, Vassilis Papaefstathiou, Sotiris Ioannidis

Proceedings of the 2013 ACM SIGSAC Conference on Computer and Communications Security, 2013

2012

Formic: Cost-efficient and Scalable Prototyping of Manycore Architectures.

Spyros Lyberis, George Kalokerinos, Michalis Lygerakis, Vassilis Papaefstathiou, Dimitrios Tsaliagkos, Manolis Katevenis, Dionisios N. Pnevmatikatos, Dimitrios S. Nikolopoulos

Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

2011

Fine-grain OpenMP runtime support with explicit communication hardware primitives.

Pranav Tendulkar, Vassilis Papaefstathiou, George Nikiforos, Stamatis G. Kavadias, Dimitrios S. Nikolopoulos, Manolis Katevenis

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Explicit Communication and Synchronization in SARC.

Manolis Katevenis, Vassilis Papaefstathiou, Stamatis G. Kavadias, Dionisios N. Pnevmatikatos, Federico Silla, Dimitrios S. Nikolopoulos

IEEE Micro, 2010

Network Processing in Multi-core FPGAs with Integrated Cache-Network Interface.

Christoforos Kachris, George Nikiforos, Stamatis G. Kavadias, Vassilis Papaefstathiou, Manolis Katevenis

Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

2009

FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability.

George Kalokerinos, Vassilis Papaefstathiou, George Nikiforos, Stamatis G. Kavadias, Manolis Katevenis, Dionisios N. Pnevmatikatos, Xiaojun Yang

Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009

2007

Prototyping Efficient Interprocessor Communication Mechanisms.

Vassilis Papaefstathiou, Dionisios N. Pnevmatikatos, Manolis Marazakis, Giorgos Kalokairinos, Aggelos Ioannou, Michael Papamichael, Stamatis G. Kavadias, Giorgos Mihelogiannakis, Manolis Katevenis

Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007

Memory-Efficient 5D Packet Classification At 40 Gbps.

Ioannis Papaefstathiou, Vassilis Papaefstathiou

Proceedings of the INFOCOM 2007. 26th IEEE International Conference on Computer Communications, 2007

Optimization and bottleneck analysis of network block I/O in commodity storage systems.

Manolis Marazakis, Vassilis Papaefstathiou, Angelos Bilas

Proceedings of the 21th Annual International Conference on Supercomputing, 2007

2006

Efficient remote block-level I/O over an RDMA-capable NIC.

Manolis Marazakis, Konstantinos Xinidis, Vassilis Papaefstathiou, Angelos Bilas

Proceedings of the 20th Annual International Conference on Supercomputing, 2006

An innovative low-cost Classification Scheme for combined multi-Gigabit IP and Ethernet Networks.

Ioannis Papaefstathiou, Vassilis Papaefstathiou

Proceedings of IEEE International Conference on Communications, 2006

A hardware-engine for layer-2 classification in low-storage, ultra-high bandwidth environments.

Vassilis Papaefstathiou, Ioannis Papaefstathiou

Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

Experiences from Debugging a PCIX-based RDMA-capable NIC.

Manolis Marazakis, Vassilis Papaefstathiou, Giorgos Kalokairinos, Angelos Bilas

Proceedings of the 2006 IEEE International Conference on Cluster Computing, 2006

2005

A Memory Efficient, 100 Gb/sec MAC Classification Engine.

Vassilis Papaefstathiou, Ioannis Papaefstathiou

Proceedings of the 30th Annual IEEE Conference on Local Computer Networks (LCN 2005), 2005

2004

Design-space exploration of the most widely used cryptography algorithms.

Ioannis Papaefstathiou, Vassilis Papaefstathiou, Christos P. Sotiriou

Microprocess. Microsystems, 2004