Vasilios I. Kelefouras
Orcid: 0000-0002-3340-3792
According to our database1,
Vasilios I. Kelefouras
authored at least 46 papers
between 2011 and 2024.
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Bibliography
2024
Int. J. Parallel Program., April, 2024
Energy Efficiency Support for Software Defined Networks: a Serverless Computing Approach.
CoRR, 2024
A Hypervisor Based Platform for the Development and Verification of Reliable Software Applications.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2024
XANDAR: An X-by-Construction Framework for Safety, Security, and Real-Time Behavior of Embedded Software Systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Proceedings of the 21st ACM International Conference on Computing Frontiers, 2024
Proceedings of the 21st ACM International Conference on Computing Frontiers, 2024
2023
IEEE Trans. Parallel Distributed Syst., December, 2023
Contactless Camera-Based Heart Rate and Respiratory Rate Monitoring Using AI on Hardware.
Sensors, 2023
SDN-Based Routing Framework for Elephant and Mice Flows Using Unsupervised Machine Learning.
Network, 2023
Towards Highly Compressed CNN Models for Human Activity Recognition in Wearable Devices.
Proceedings of the Signal Processing: Algorithms, 2023
Proceedings of the Architecture of Computing Systems - 36th International Conference, 2023
2022
IEEE Trans. Parallel Distributed Syst., 2022
Workflow simulation and multi-threading aware task scheduling for heterogeneous computing.
J. Parallel Distributed Comput., 2022
Int. J. Parallel Program., 2022
Anatomy of Deep Learning Image Classification and Object Detection on Commercial Edge Devices: A Case Study on Face Mask Detection.
IEEE Access, 2022
XANDAR: A holistic Cybersecurity Engineering Process for Safety-critical and Cyber-physical Systems.
Proceedings of the 95th IEEE Vehicular Technology Conference, 2022
A Design Space Exploration Methodology for Enabling Tensor Train Decomposition in Edge Devices.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2022
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
XANDAR: Exploiting the X-by-Construction Paradigm in Model-based Development of Safety-critical Systems.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the 12th International Conference on Cloud Computing and Services Science, 2022
2021
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2021
Proceedings of the Intelligent Computing, 2021
Proceedings of the 10th Mediterranean Conference on Embedded Computing, 2021
XANDAR: X-by-Construction Design framework for Engineering Autonomous & Distributed Real-time Embedded Software Systems.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021
2019
A methodology correlating code optimizations with data memory accesses, execution time and energy consumption.
J. Supercomput., 2019
2018
Combining Software Cache Partitioning and Loop Tiling for Effective Shared Cache Management.
ACM Trans. Embed. Comput. Syst., 2018
Workflow Simulation Aware and Multi-threading Effective Task Scheduling for Heterogeneous Computing.
Proceedings of the 25th IEEE International Conference on High Performance Computing, 2018
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018
2017
A methodology pruning the search space of six compiler transformations by addressing them together as one problem and by exploiting the hardware architecture details.
Computing, 2017
Cache Partitioning + Loop Tiling: A Methodology for Effective Shared Cache Management.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
2016
ACM Trans. Design Autom. Electr. Syst., 2016
A high-performance matrix-matrix multiplication methodology for CPU and GPU architectures.
J. Supercomput., 2016
J. Circuits Syst. Comput., 2016
2015
A methodology for speeding up matrix vector multiplication for single/multi-core architectures.
J. Supercomput., 2015
A methodology for speeding up loop kernels by exploiting the software information and the memory architecture.
Comput. Lang. Syst. Struct., 2015
2014
A Methodology for Speeding up MVM for Regular, Toeplitz and Bisymmetric Toeplitz Matrices.
J. Signal Process. Syst., 2014
A Matrix-Matrix Multiplication methodology for single/multi-core architectures using SIMD.
J. Supercomput., 2014
A methodology for speeding up edge and line detection algorithms focusing on memory architecture utilization.
J. Supercomput., 2014
ACM Trans. Archit. Code Optim., 2014
2013
Near-optimal and scalable intrasignal in-place optimization for non-overlapping and irregular access schemes.
ACM Trans. Design Autom. Electr. Syst., 2013
Near-Optimal Microprocessor and Accelerators Codesign with Latency and Throughput Constraints.
ACM Trans. Archit. Code Optim., 2013
ACM Comput. Surv., 2013
2012
ACM Trans. Reconfigurable Technol. Syst., 2012
J. Supercomput., 2012
A template-based methodology for efficient microprocessor and FPGA accelerator co-design.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012
2011
A Methodology for Speeding Up Fast Fourier Transform Focusing on Memory Architecture Utilization.
IEEE Trans. Signal Process., 2011