Vasileios Porpodas
According to our database1,
Vasileios Porpodas
authored at least 22 papers
between 2007 and 2020.
Collaborative distances:
Collaborative distances:
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On csauthors.net:
Bibliography
2020
Proceedings of the CC '20: 29th International Conference on Compiler Construction, 2020
2019
CoRR, 2019
Proceedings of the Languages and Compilers for Parallel Computing, 2019
Super-Node SLP: Optimized Vectorization for Code Sequences Containing Operators and Their Inverse Elements.
Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2019
2018
Proceedings of the 2018 International Symposium on Code Generation and Optimization, 2018
Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques, 2018
2017
Proceedings of the Fourth Workshop on the LLVM Compiler Infrastructure in HPC, 2017
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017
2016
Proceedings of the 2016 International Conference on Supercomputing, 2016
Proceedings of the 2016 International Conference on Compilers, 2016
2015
Proceedings of the 13th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2015
Proceedings of the 2015 International Conference on Parallel Architectures and Compilation, 2015
2013
Proceedings of the SIGPLAN/SIGBED Conference on Languages, 2013
Proceedings of the Languages and Compilers for Parallel Computing, 2013
Proceedings of the Languages and Compilers for Parallel Computing, 2013
Proceedings of the 27th IEEE International Symposium on Parallel and Distributed Processing, 2013
CAeSaR: Unified cluster-assignment scheduling and communication reuse for clustered VLIW processors.
Proceedings of the International Conference on Compilers, 2013
2012
UCIFF: Unified Cluster Assignment Instruction Scheduling and Fast Frequency Selection for Heterogeneous Clustered VLIW Cores.
Proceedings of the Languages and Compilers for Parallel Computing, 2012
Cooperative partitioning: Energy-efficient cache partitioning for high-performance CMPs.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012
2010
Decoupled Processors Architecture for Accelerating Data Intensive Applications using Scratch-Pad Memory Hierarchy.
J. Signal Process. Syst., 2010
2009
Low-power architecture with scratch-pad memory for accelerating embedded applications with run-time reuse.
IET Comput. Digit. Tech., 2009
2007
Interactive presentation: A decoupled architecture of processors with scratch-pad memory hierarchy.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007