Varadan Savulimedu Veeravalli

According to our database, Varadan Savulimedu Veeravalli authored at least 15 papers between 2012 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

A versatile architecture for long-term monitoring of single-event transient durations.

Varadan Savulimedu Veeravalli, Andreas Steininger, Ulrich Schmid

Microprocess. Microsystems, 2017

Setup for an Experimental Study of Radiation Effects in 65nm CMOS.

Bernhard Fritz, Andreas Steininger, Václav Simek, Varadan Savulimedu Veeravalli

Proceedings of the Euromicro Conference on Digital System Design, 2017

A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case Study.

Marko S. Andjelkovic, Milos Krstic, Rolf Kraemer, Varadan Savulimedu Veeravalli, Andreas Steininger

Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016

Study of a delayed single-event effect in the Muller C-element.

Varadan Savulimedu Veeravalli, Andreas Steininger

Proceedings of the 21th IEEE European Test Symposium, 2016

Design and Physical Implementation of a Target ASIC for SET Experiments.

Varadan Savulimedu Veeravalli, Andreas Steininger

Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

2015

Building reliable systems-on-chip in nanoscale technologies.

Andreas Steininger, Horst Zimmermann, Axel Jantsch, Michael Hofbauer, Ulrich Schmid, Kurt Schweiger, Varadan Savulimedu Veeravalli

Elektrotech. Informationstechnik, 2015

Reliable and Continuous Measurement of SET Pulse Widths.

Varadan Savulimedu Veeravalli, Andreas Steininger

Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

2014

Measuring SET pulsewidths in logic gates using digital infrastructure.

Varadan Savulimedu Veeravalli, Andreas Steininger, Ulrich Schmid

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Architecture for monitoring SET propagation in 16-bit Sklansky adder.

Varadan Savulimedu Veeravalli, Andreas Steininger

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example.

Andreas Steininger, Varadan Savulimedu Veeravalli, Dan Alexandrescu, Enrico Costenaro, Lorena Anghel

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013

An infrastructure for accurate characterization of single-event transients in digital circuits.

Varadan Savulimedu Veeravalli, Thomas Polzer, Ulrich Schmid, Andreas Steininger, Michael Hofbauer, Kurt Schweiger, Horst Dietrich, Kerstin Schneider-Hornstein, Horst Zimmermann, Kay-Obbe Voss, Bruno Merk, Michael Hajek

Microprocess. Microsystems, 2013

Modular Redundancy in a GALS System Using Asynchronous Recovery Links.

Jakob Lechner, Varadan Savulimedu Veeravalli

Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems, 2013

2012

Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip.

Varadan Savulimedu Veeravalli, Thomas Polzer, Andreas Steininger, Ulrich Schmid

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Protecting an Asynchronous NoC against Transient Channel Faults.

Syed Rameez Naqvi, Varadan Savulimedu Veeravalli, Andreas Steininger

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Radiation-tolerant combinational gates - an implementation based comparison.

Varadan Savulimedu Veeravalli, Andreas Steininger

Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012