Van D. Nguyen

Orcid: 0000-0001-6924-4298

According to our database1, Van D. Nguyen authored at least 4 papers between 2022 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

2022
2023
2024
2025
0
1
2
3
1
1
1
1

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2025
Benchmarking of Scaled Majority-Logic-Synthesized Spintronic Circuits Based on Magnetic Tunnel Junction Transducers.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2025

2024
Extremely Scaled Perpendicular SOT-MRAM Array Integration on 300mm Wafer.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2022
Challenges and targets of MRAM-enabled scaled spintronic logic circuits.
CoRR, 2022

Selective operations of multi-pillar SOT-MRAM for high density and low power embedded memories.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022


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