Vamsi Boppana

According to our database, Vamsi Boppana authored at least 36 papers between 1993 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2019

Xilinx First 7nm Device: Versal AI Core (VC1902).

Sagheer Ahmad, Sridhar Subramanian, Vamsi Boppana, Shankar Lakka, Fu-Hing Ho, Tomai Knopp, Juanjo Noguera, Gaurav Singh, Ralph Wittig

Proceedings of the 2019 IEEE Hot Chips 31 Symposium (HCS), 2019

2016

A 16-nm Multiprocessing System-on-Chip Field-Programmable Gate Array Platform.

Sagheer Ahmad, Vamsi Boppana, Ilya Ganusov, Vinod Kathail, Vidya Rajagopalan, Ralph Wittig

IEEE Micro, 2016

2015

UltraScale+ MPSoC and FPGA families.

Vamsi Boppana, Sagheer Ahmad, Ilya Ganusov, Vinod Kathail, Vidya Rajagopalan, Ralph Wittig

Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

2011

Xilinx Zynq-7000 EPP: An extensible processing platform family.

Vidya Rajagopalan, Vamsi Boppana, Sandeep Dutta, Brad Taylor, Ralph Wittig

Proceedings of the 2011 IEEE Hot Chips 23 Symposium (HCS), 2011

2008

Implementing the Best Processor Cores.

Vamsi Boppana, Rahoul Varma, S. Balajee

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Low power chips: a fabless asic perspective.

Shashank Bhonge, Vamsi Boppana

Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

2005

Transistor-Level Optimization of Digital Designs with Flex Cells.

Rob Roy, Debashis Bhattacharya, Vamsi Boppana

Computer, 2005

2004

Accurate pre-layout estimation of standard cell characteristics.

Hiroaki Yoshida, Kaushik De, Vamsi Boppana

Proceedings of the 41th Design Automation Conference, 2004

2003

Fault equivalence identification in combinational circuits using implication and evaluation techniques.

M. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

2002

Design for Verification at the Register Transfer Level.

Indradeep Ghosh, Krishna Sekar, Vamsi Boppana

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

2001

Fault-diagnosis-based technique for establishing RTL and gate-levelcorrespondences.

Srivaths Ravi, Indradeep Ghosh, Vamsi Boppana, Niraj K. Jha

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Fault Equivalence Identification Using Redundancy Information and Static and Dynamic Extraction.

M. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Cellular automata as a built in self test structure.

Biplab K. Sikdar, Debesh K. Das, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee, Parimal Pal Chaudhuri

Proceedings of ASP-DAC 2001, 2001

2000

Testing, Verification, and Diagnosis in the Presence of Unknowns.

Ankur Jain, Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Michael S. Hsiao

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Theory and Application of GF(2p) Cellular Automata as On-chip Test Pattern Generator.

Biplab K. Sikdar, Kolin Paul, Gosta Pada Biswas, Parimal Pal Chaudhuri, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Hierarchical Error Diagnosis Targeting RTL Circuits.

Vamsi Boppana, Indradeep Ghosh, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

A Technique for Identifying RTL and Gate-Level Correspondences.

Srivaths Ravi, Niraj K. Jha, Indradeep Ghosh, Vamsi Boppana

Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

1999

On the Evaluation of Arbitrary Defect Coverage of Test Sets.

Ankur Jain, Michael S. Hsiao, Vamsi Boppana, Masahiro Fujita

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Implication and Evaluation Techniques for Proving Fault Equivalence.

M. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Multiple Error Diagnosis Based on Xlists.

Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Pradeep Bollineni

Proceedings of the 36th Conference on Design Automation, 1999

Model Checking Based on Sequential ATPG.

Vamsi Boppana, Sreeranga P. Rajan, Koichiro Takayama, Masahiro Fujita

Proceedings of the Computer Aided Verification, 11th International Conference, 1999

1998

Modeling the unknown! Towards model-independent fault and error diagnosis.

Vamsi Boppana, Masahiro Fujita

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Dynamic fault collapsing and diagnostic test pattern generation for sequential circuits.

Vamsi Boppana, W. Kent Fuchs

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

1997

State Information-Based Solutions for Sequential Circuit Diagnosis and Testing

Vamsi Boppana

PhD thesis, 1997

Diagnostic Test Pattern Generation for Sequential Circuits.

Ismed Hartanto, Vamsi Boppana, Janak H. Patel, W. Kent Fuchs

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Characterization and Implicit Identification of Sequential Indistinguishability.

Vamsi Boppana, Ismed Hartanto, W. Kent Fuchs

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1996

Full fault dictionary storage based on labeled tree encoding.

Vamsi Boppana, Ismed Hartanto, W. Kent Fuchs

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Diagnostic Fault Equivalence Identification Using Redundancy Information and Structural Analysis.

Ismed Hartanto, Vamsi Boppana, W. Kent Fuchs

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Partial Scan Design Based on State Transition Modeling.

Vamsi Boppana, W. Kent Fuchs

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Identification of unsettable flip-flops for partial scan and faster ATPG.

Ismed Hartanto, Vamsi Boppana, W. Kent Fuchs

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Integrated fault diagnosis targeting reduced simulation.

Vamsi Boppana, W. Kent Fuchs

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Fault Diagnosis Using State Information.

Vamsi Boppana, Ismed Hartanto, W. Kent Fuchs

Proceedings of the Digest of Papers: FTCS-26, 1996

A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs.

Vamsi Boppana, Prashant Saxena, Prithviraj Banerjee, W. Kent Fuchs, C. L. Liu

Proceedings of the Euro-Par '96 Parallel Processing, 1996

1994

A CAD Tool for Design of On-Chip Store & Generate Scheme.

Sukumar Nandi, Vamsi Boppana, Parimal Pal Chaudhuri

Proceedings of the Seventh International Conference on VLSI Design, 1994

Fault dictionary compaction by output sequence removal.

Vamsi Boppana, W. Kent Fuchs

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

1993

Delay Fault Test Generation with Cellular Automata.

Sukumar Nandi, Vamsi Boppana, Supratik Chakraborty, Parimal Pal Chaudhuri, Samir Roy

Proceedings of the Sixth International Conference on VLSI Design, 1993