Vallabhuni Vijay

Orcid: 0000-0002-9070-919X

According to our database1, Vallabhuni Vijay authored at least 12 papers between 2021 and 2024.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

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Bibliography

2024
Design and analysis of a novel compact quaternary adder.
Int. J. Syst. Assur. Eng. Manag., July, 2024

State-of-art design: data selectors using quantum-dot cellular automata.
Int. J. Syst. Assur. Eng. Manag., March, 2024

1-bit full adder design using next generation semiconductor devices and performance benchmarking at low supply voltages.
Int. J. Syst. Assur. Eng. Manag., March, 2024

2023
State of the art design of adder modules: performance validation of GDI methodology for energy harvesting applications.
Int. J. Syst. Assur. Eng. Manag., December, 2023

Design and performance analysis of low power and energy-efficient vedic multipliers.
Int. J. Syst. Assur. Eng. Manag., June, 2023

2022
A hierarchical image matting model for blood vessel segmentation in retinal images.
Int. J. Syst. Assur. Eng. Manag., 2022

A VLSI design of clock gated technique based ADC lock-in amplifier.
Int. J. Syst. Assur. Eng. Manag., 2022

Numerical analysis of various plasmonic MIM/MDM slot waveguide structures.
Int. J. Syst. Assur. Eng. Manag., 2022

Double-threshold energy detection: noisy environment applied cognitive radio.
Int. J. Syst. Assur. Eng. Manag., 2022

2021
Road Identification Through Efficient Edge Segmentation Based on Morphological Operations.
Traitement du Signal, 2021

ECG performance validation using operational transconductance amplifier with bias current.
Int. J. Syst. Assur. Eng. Manag., 2021

Novel All-Pass Section for High-Performance Signal Processing Using CMOS DCCII.
Proceedings of the IEEE Region 10 Conference, 2021


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