Valerio Tenace

CoRR, 2024

AIvril: AI-Driven RTL Generation With Verification In-The-Loop.

[BibT_eX]

[DOI]

Mubashir ul Islam

Humza Sami

CoRR, 2024

2021

Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

NEMO-CNN: An Efficient Near-Memory Accelerator for Convolutional Neural Networks.

[BibT_eX]

[DOI]

Grant Brown

Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021

2020

Logic Synthesis of Pass-Gate Logic Circuits With Emerging Ambipolar Technologies.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2019

Layer-Wise Compressive Training for Convolutional Neural Networks.

[BibT_eX]

[DOI]

Matteo Grimaldi

Future Internet, 2019

SAID: A Supergate-Aided Logic Synthesis Flow for Memristive Crossbars.

[BibT_eX]

[DOI]

Roberto Giorgio Rizzo

Debjyoti Bhattacharjee

Anupam Chattopadhyay

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Energy-Efficient Convolutional Neural Networks via Recurrent Data Reuse.

[BibT_eX]

[DOI]

Luca Mocerino

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

Quasi-exact logic functions through classification trees.

[BibT_eX]

[DOI]

Integr., 2018

Inferential Logic: a Machine Learning Inspired Paradigm for Combinational Circuits.

[BibT_eX]

[DOI]

Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Multiplication by Inference using Classification Trees: A Case-Study Analysis.

[BibT_eX]

[DOI]

Roberto Giorgio Rizzo

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A compression-driven training framework for embedded deep neural networks.

[BibT_eX]

[DOI]

Proceedings of the Workshop on INTelligent Embedded Systems Architectures and Applications, 2018

2017

Activation-Kernel Extraction through Machine Learning.

[BibT_eX]

[DOI]

Proceedings of the New Generation of CAS, 2017

2016

CAD Tools for Graphene-Based Electronic Circuits.

[BibT_eX]

[DOI]

PhD thesis, 2016

Quasi-Adiabatic Logic Arrays for Silicon and Beyond-Silicon Energy-Efficient ICs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2016

Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic Circuits.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability, 2016

Multi-function logic synthesis of silicon and beyond-silicon ultra-low power pass-gates circuits.

[BibT_eX]

[DOI]

Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon technologies.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Graphene-PLA (GPLA): a Compact and Ultra-Low Power Logic Array Architecture.

[BibT_eX]

[DOI]

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2015

Ultra-low power circuits using graphene p-n junctions and adiabatic computing.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2015

Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization.

[BibT_eX]

[DOI]