Valerio Pica

Orcid: 0009-0004-2468-4029

According to our database1, Valerio Pica authored at least 3 papers in 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Soft and Hard Error-Correction Techniques in STT-MRAM.
IEEE Des. Test, October, 2024

Extremely Scaled Perpendicular SOT-MRAM Array Integration on 300mm Wafer.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

A novel test and analysis scheme to elucidate tail bit characteristics in STT-MRAM arrays.
Proceedings of the IEEE International Memory Workshop, 2024


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