Valerio Mazzaro
Orcid: 0000-0002-2512-550X
According to our database1,
Valerio Mazzaro
authored at least 9 papers
between 2019 and 2024.
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Timeline
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2024
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Bibliography
2024
10.4 A 45.5fs-Integrated-Random-Jitter and -75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional, Horn, and Wandering Spurs.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A Family of ΔΣ Modulators With High Spur Immunity and Low Folded Nonlinearity Noise When Used in Fractional- Frequency Synthesizers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Immunity of ENOP-based Fractional-N Frequency Synthesizer to Wandering and Horn Spurs.
Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022
2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
2020
IEEE Trans. Circuits Syst. II Express Briefs, 2020
A Curious Result concerning Spur Generation in MASH 1-1-1 based Fractional-N CP-PLLs with a Second-Order Nonlinearity.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019