Valerio Guarnieri
According to our database1,
Valerio Guarnieri
authored at least 20 papers
between 2008 and 2016.
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Collaborative distances:
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Bibliography
2016
2015
J. Electron. Test., 2015
2014
IEEE Trans. Computers, 2014
Proceedings of the 15th Latin American Test Workshop, 2014
A cross-level verification methodology for digital IPs augmented with embedded timing monitors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2012
J. Electron. Test., 2012
HDTLib: an efficient implementation of SystemC data types for fast simulation at different abstraction levels.
Des. Autom. Embed. Syst., 2012
Redesign and Verification of RTL IPs through RTL-to-TLM Abstraction and TLM Synthesis.
Proceedings of the 13th International Workshop on Microprocessor Test and Verification, 2012
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012
FAST-GP: An RTL functional verification framework based on fault simulation on GP-GPUs.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012
Reduced-Complexity Transition-Fault Test Generation for Non-scan Circuits through High-Level Mutant Injection.
Proceedings of the 21st IEEE Asian Test Symposium, 2012
2011
Proceedings of the 12th Latin American Test Workshop, 2011
Proceedings of the 2011 Forum on Specification & Design Languages, 2011
Proceedings of the 16th European Test Symposium, 2011
2010
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010
2008
Proceedings of the 2008 East-West Design & Test Symposium, 2008