Valerij V. Saposhnikov

Affiliations:
  • Railway Transportation State University, St. Petersburg, Russia


According to our database1, Valerij V. Saposhnikov authored at least 11 papers between 1996 and 2004.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2004
Necessary and Sufficient Conditions for the Existence of Totally Self-Checking Circuits.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

Complementary Circuits for On-Line Detection for 1-out-of-3 Codes.
Proceedings of the ARCS 2004, 2004

2000
New Self-dual Circuits for Error Detection and Testing.
VLSI Design, 2000

New Self-Checking Circuits by Use of Berger-Codes.
Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000

A New Method for Concurrent Checking by Use of a 1-out-of-4 Code.
Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000

A New Method of Redundancy Addition for Circuit Optimization.
Proceedings of the 26th EUROMICRO 2000 Conference, 2000

1999
Experimental Results for Self-Dual Multi-Output Combinational Circuits.
J. Electron. Test., 1999

1998
Self-Checking Combinational Circuits with Unidirectionally Independent Outputs.
VLSI Design, 1998

A New Design Method for Self-Checking Unidirectional Combinational Circuits.
J. Electron. Test., 1998

Self-Dual Duplication for Error Detection.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1996
Self-dual parity checking-A new method for on-line testing.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996


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