Valerie Lines

According to our database, Valerie Lines authored at least 3 papers between 1991 and 2005.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2005

A 1GHz embedded DRAM macro and fully programmable BIST with at-speed bitmap capability.

Valerie Lines, Robert McKenzie, Hakjune Oh, Hong-Beom Pyeon, Matthew Dunn, Susan Palapar, Susan Coleman, Peter Nyasulu, Tony Mai, Seanna Pike, John McCready, Jody Defazio, Jin-Ki Kim, Robert Penchuk, Zvika Greenfield, Fredy Lange, Alberto Mandler, Eric C. Jones, Matthew Silverstein

Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005

2000

66MHz 2.3M Ternary Dynamic Content Addressable Memory.

Valerie Lines, Abdullah Ahmed, Peter Ma, Stanley Ma, Robert McKenzie, Hong-Seok Kim, Cynthia Mar

Proceedings of the 8th IEEE International Workshop on Memory Technology, 2000

1991

High-speed, high-reliability circuit design for megabit DRAM.

Peter Gillingham, Richard C. Foss, Valerie Lines, Gregg Shimokura, Tomasz Wojcicki

IEEE J. Solid State Circuits, August, 1991