Valeria Garofalo

According to our database1, Valeria Garofalo authored at least 11 papers between 2007 and 2014.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2014
Truncated squarer with minimum mean-square error.
Microelectron. J., 2014

2011
Design of Fixed-Width Multipliers With Linear Compensation Function.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Analytical Calculation of the Maximum Error for a Family of Truncated Multipliers Providing Minimum Mean Square Error.
IEEE Trans. Computers, 2011

2010
Truncated Binary Multipliers With Variable Correction and Minimum Mean Square Error.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Fixed-width CSD multipliers with minimum mean square error.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A novel truncated squarer with linear compensation function.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

High-speed differential resistor ladder for A/D converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2008
Fixed-width multipliers for the implementation of efficient digital FIR filters.
Microelectron. J., 2008

Constrained piecewise polinomial approximation for hardware implementation of elementary functions.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Low error truncated multipliers for DSP applications.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007
Code compression for ARM7 embedded systems.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007


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