Valentina Ciriani

Majid Haghparast

Quantum Inf. Process., August, 2024

2023

XOR-AND-XOR Logic Forms for Autosymmetric Functions and Applications to Quantum Computing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2023

Novel qutrit circuit design for multiplexer, De-multiplexer, and decoder.

[BibT_eX]

[DOI]

Quantum Inf. Process., 2023

Quaternary Reversible Circuit Optimization for Scalable Multiplexer and Demultiplexer.

[BibT_eX]

[DOI]

IEEE Access, 2023

Compact Quantum Circuits for Dimension Reducible Functions.

[BibT_eX]

[DOI]

Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

2022

Exploiting Symmetrization and D-Reducibility for Approximate Logic Synthesis.

[BibT_eX]

[DOI]

Tiziano Villa

IEEE Trans. Computers, 2022

Multiplicative Complexity of XOR Based Regular Functions.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2022

ADD-based Spectral Analysis of Probing Security.

[BibT_eX]

[DOI]

Maria Chiara Molteni

Vittorio Zaccaria

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

On the Optimal OBDD Representation of 2-XOR Boolean Affine Spaces.

[BibT_eX]

[DOI]

Padmanabhan Balasubramanian

Marco Longhi

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

A Boolean Heuristic for Disjoint SOP Synthesis.

[BibT_eX]

[DOI]

Tiziano Villa

Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

Autosymmetry of Incompletely Specified Functions.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Stuck-At Fault Mitigation of Emerging Technologies Based Switching Lattices.

[BibT_eX]

[DOI]

J. Electron. Test., 2020

Computing the full quotient in bi-decomposition by approximation.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Multiplicative Complexity of Autosymmetric Functions: Theory and Applications to Security.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Boolean Minimization of Projected Sums of Products via Boolean Relations.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2019

An OBDD-Based Technique for the Efficient Synthesis of Garbled Circuits.

[BibT_eX]

[DOI]

Proceedings of the Security and Trust Management - 15th International Workshop, 2019

Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model.

[BibT_eX]

[DOI]

Proceedings of the IEEE Latin American Test Symposium, 2019

Testability of Switching Lattices in the Cellular Fault Model.

[BibT_eX]

[DOI]

Luca Frontini

Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

Approximate Logic Synthesis by Symmetrization.

[BibT_eX]

[DOI]

Tiziano Villa

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

Composition of switching lattices for regular and for decomposed functions.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2018

Enhancing logic synthesis of switching lattices by generalized Shannon decomposition methods.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2018

Testability of Switching Lattices in the Stuck at Fault Model.

[BibT_eX]

[DOI]

Luca Frontini

Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Integrated Synthesis Methodology for Crossbar Arrays.

[BibT_eX]

[DOI]

Muhammed Ceylan Morgül

Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

2017

Logic synthesis and testing techniques for switching nano-crossbar arrays.

[BibT_eX]

[DOI]

Mehdi Baradaran Tahoori

Microprocess. Microsystems, 2017

A multiple valued logic approach for the synthesis of garbled circuits.

[BibT_eX]

[DOI]

Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

Exploiting Quantum Gates in Secure Computation.

[BibT_eX]

[DOI]

Proceedings of the Euromicro Conference on Digital System Design, 2017

Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis.

[BibT_eX]

[DOI]

Proceedings of the Euromicro Conference on Digital System Design, 2017

Computing with nano-crossbar arrays: Logic synthesis and fault tolerance.

[BibT_eX]

[DOI]

Mustafa Altun

Mehdi Baradaran Tahoori

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

Index-Resilient Zero-Suppressed BDDs: Definition and Operations.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2016

Synthesis on switching lattices of Dimension-reducible Boolean functions.

[BibT_eX]

[DOI]

Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Logic Synthesis for Switching Lattices by Decomposition with P-Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer.

[BibT_eX]

[DOI]

Mehdi Baradaran Tahoori

Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

2015

On the error resilience of ordered binary decision diagrams.

[BibT_eX]

[DOI]

Lorenzo Lago

Theor. Comput. Sci., 2015

Using Flexibility in P-Circuits by Boolean Relations.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2015

Biconditional-BDD Ordering for Autosymmetric Functions.

[BibT_eX]

[DOI]

Gabriella Trucco

Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Bi-Decomposition Using Boolean Relations.

[BibT_eX]

[DOI]

Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

2014

Autosymmetric and Dimension Reducible Multiple-Valued Functions.

[BibT_eX]

[DOI]

J. Multiple Valued Log. Soft Comput., 2014

Zero-Suppressed Binary Decision Diagrams Resilient to Index Faults.

[BibT_eX]

[DOI]

Proceedings of the Theoretical Computer Science, 2014

Radiation-tolerant standard cell synthesis using double-rail redundant approach.

[BibT_eX]

[DOI]

Luca Frontini

Valentino Liberali

Seyedruhollah Shojaii

Alberto Stabile

Gabriella Trucco

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2-SPP Approximate Synthesis for Error Tolerant Applications.

[BibT_eX]

[DOI]

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

2013

Compact DSOP and Partial DSOP Forms.

[BibT_eX]

[DOI]

Theory Comput. Syst., 2013

SOP restructuring by exploiting don't cares.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2013

Minimization of EP-SOPs via Boolean relations.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Error resilient OBDDs.

[BibT_eX]

[DOI]

Lorenzo Lago

Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

Minimization of P-circuits using Boolean relations.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

2012

An OBDD approach to enforce confidentiality and visibility constraints in data publishing.

[BibT_eX]

[DOI]

Giovanni Livraga

J. Comput. Secur., 2012

Synthesis of P-circuits for logic restructuring.

[BibT_eX]

[DOI]

Integr., 2012

Projected Don't Cares.

[BibT_eX]

[DOI]

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011

Dimension-reducible Boolean functions based on affine spaces.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2011

Selective data outsourcing for enforcing privacy.

[BibT_eX]

[DOI]

J. Comput. Secur., 2011

Autosymmetric Multiple-Valued Functions: Theory and Spectral Characterization.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011

An approximation algorithm for cofactoring-based synthesis.

[BibT_eX]

[DOI]

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Enforcing Confidentiality and Data Visibility Constraints: An OBDD Approach.

[BibT_eX]

[DOI]

Giovanni Livraga

Proceedings of the Data and Applications Security and Privacy XXV, 2011

Compact and Testable Circuits for Regular Functions.

[BibT_eX]

[DOI]

Proceedings of the ARCS 2011, 2011

2010

Combining fragmentation and encryption to protect privacy in data storage.

[BibT_eX]

[DOI]

ACM Trans. Inf. Syst. Secur., 2010

Logic synthesis and testability of D-reducible functions.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Fun at a Department Store: Data Mining Meets Switching Theory.

[BibT_eX]

[DOI]

Proceedings of the Fun with Algorithms, 5th International Conference, 2010

2009

Fragmentation Design for Efficient Query Execution over Sensitive Distributed Databases.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE International Conference on Distributed Computing Systems (ICDCS 2009), 2009

Keep a Few: Outsourcing Data While Maintaining Confidentiality.

[BibT_eX]

[DOI]

Proceedings of the Computer Security, 2009

Logic Minimization and Testability of 2SPP-P-Circuits.

[BibT_eX]

[DOI]

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Enforcing Confidentiality Constraints on Sensitive Databases with Lightweight Trusted Clients.

[BibT_eX]

[DOI]

Proceedings of the Data and Applications Security XXIII, 2009

On decomposing Boolean functions via extended cofactoring.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

2008

<i>k</i> -Anonymous Data Mining: A Survey.

[BibT_eX]

[DOI]

Proceedings of the Privacy-Preserving Data Mining - Models and Algorithms, 2008

The optimization of kEP-SOPs: Computational complexity, approximability and experiments.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2008

Logic Minimization and Testability of 2-SPP Networks.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Synthesis of Autosymmetric Functions in a New Three-Level Form.

[BibT_eX]

[DOI]

Theory Comput. Syst., 2008

On the construction of small fully testable circuits with low depth.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2008

A Comparison between Two Logic Synthesis Forms from Digital Switching Noise Viewpoint.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

On Projecting Sums of Products.

[BibT_eX]

[DOI]

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007

<i>k</i>-Anonymity.

[BibT_eX]

[DOI]

Proceedings of the Secure Data Management in Decentralized Systems, 2007

Microdata Protection.

[BibT_eX]

[DOI]

Proceedings of the Secure Data Management in Decentralized Systems, 2007

A data structure for a sequence of string accesses in external memory.

[BibT_eX]

[DOI]

ACM Trans. Algorithms, 2007

An approximation algorithm for fully testable kEP-SOP networks.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Fragmentation and Encryption to Enforce Privacy in Data Storage.

[BibT_eX]

[DOI]

Proceedings of the Computer Security, 2007

2006

Testability of SPP Three-Level Logic Networks in Static Fault Models.

[BibT_eX]

[DOI]

Rolf Drechsler

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Exploiting Regularities for Boolean Function Synthesis.

[BibT_eX]

[DOI]

Theory Comput. Syst., 2006

Logic Synthesis of EXOR Projected Sum of Products.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006

EXOR Projected Sum of Products.

[BibT_eX]

[DOI]

Proceedings of the IFIP VLSI-SoC 2006, 2006

DRedSOP: Synthesis of a New Class of Regular Functions.

[BibT_eX]

[DOI]

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Efficient minimization of fully testable 2-SPP networks.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2004

Room allocation: a polynomial subcase of the quadratic assignment problem.

[BibT_eX]

[DOI]

Nadia Pisanti

Discret. Appl. Math., 2004

2003

Synthesis of SPP three-level logic networks using affine spaces.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Three-level logic minimization based on function regularities.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Synthesis of integer multipliers in sum of pseudoproducts form.

[BibT_eX]

[DOI]

Fabrizio Luccio

Linda Pagli

Integr., 2003

Stuck-At-Fault Testability of SPP Three-Level Logic Forms.

[BibT_eX]

[DOI]

Rolf Drechsler

Proceedings of the VLSI-SOC: From Systems to Chips, 2003

Testability of SPP Three-Level Logic Networks.

[BibT_eX]

Rolf Drechsler

Proceedings of the IFIP VLSI-SoC 2003, 2003

2002

Implicit Test of Regularity for Not Completely Specified Boolean Functions.

[BibT_eX]

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Static Optimality Theorem for External Memory String Access.

[BibT_eX]

[DOI]

Proceedings of the 43rd Symposium on Foundations of Computer Science (FOCS 2002), 2002

Fast three-level logic minimization based on autosymmetry.

[BibT_eX]

[DOI]

Proceedings of the 39th Design Automation Conference, 2002

2001

Logic Minimization using Exclusive OR Gates.

[BibT_eX]

[DOI]