Valentina Andreeva

According to our database, Valentina Andreeva authored at least 13 papers between 2002 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2022

Deriving FSM-based tests using $a, b-\text{faults}$ for Logic Circuits.

Andrey Laputenko, Nina Yevtushenko, Valentina Andreeva, Anzhela Yu. Matrosova

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

2021

SAT Solvers Application of Deriving All Test Pairs Detecting Robust Testable PDFs.

Anjela Yu. Matrosova, Valentina Andreeva, V. Tychinskiy

Proceedings of the IEEE East-West Design & Test Symposium, 2021

2019

Deriving Low Power Test Sequences Detecting Robust Testable PDFs.

Anjela Yu. Matrosova, Valentina Andreeva, V. Tychinskiy

Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019

2018

Fault-Tolerant Synchronous FSM Network Design for Path Delay Faults.

Sergey Ostanin, Valentina Andreeva, Natalia Butorina, D. Tretyakov

Proceedings of the 2018 IEEE East-West Design & Test Symposium, 2018

2017

Finding the shortest transfer sequence of sequential circuit based on simplified ROBDDs.

Valentina Andreeva, Semyon Chernyshov

Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

2016

ROBDDs application for finding the shortest transfer sequence of sequential circuit or only revealing existence of this sequence without deriving the sequence itself.

Anzhela Yu. Matrosova, Valentina Andreeva, Alexey Melnikov

Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

Patching circuit design based on reserved CLBs.

Anjela Yu. Matrosova, Sergey Ostanin, Valentina Andreeva

Proceedings of the IEEE International Conference on Automation, 2016

2015

Fully delay and multiple stuck-at faults testable FSM design.

Anzhela Yu. Matrosova, Valentina Andreeva, V. Tomkov

Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015

2014

Decomposition tree - based compaction procedure with iteration steps for interconversional layouts of tasks.

Valentina Andreeva, Kirill A. Sorudeykin

Proceedings of the 2014 East-West Design & Test Symposium, 2014

2013

A research of heuristic optimization approaches to the test set compaction procedure based on a decomposition tree for combinational circuits.

Valentina Andreeva, Kirill A. Sorudeykin

Proceedings of the East-West Design & Test Symposium, 2013

2011

Test set compaction procedure for combinational circuits based on decomposition tree.

Valentina Andreeva

Proceedings of the 9th East-West Design & Test Symposium, 2011

2010

Test minimization technique for multiple stuck-at faults of combinational circuit.

Valentina Andreeva

Proceedings of the 2010 East-West Design & Test Symposium, 2010

2002

Survivable Discrete Circuits Design.

Anzhela Yu. Matrosova, Valentina Andreeva, Yu. Sedov

Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002