Valentin Gherman

Cyrille Laffond

Proceedings of the 42nd IEEE VLSI Test Symposium, 2024

2023

Benefits of Design Assist Techniques on Performances and Reliability of a RRAM Macro.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Memory Workshop, 2023

2020

On Using Approximate Computing to Build an Error Detection Scheme for Arithmetic Circuits.

[BibT_eX]

[DOI]

J. Electron. Test., 2020

Binary Linear ECCs Optimized for Bit Inversion in Memories with Asymmetric Error Probabilities.

[BibT_eX]

[DOI]

Bastien Giraud

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2018

Evaluation of the temperature influence on SEU vulnerability of DICE and 6T-SRAM cells.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

Is aproximate computing suitable for selective hardening of arithmetic circuits?

[BibT_eX]

[DOI]

Bastien Deveautour

Arnaud Virazel

Patrick Girard

Serge Pravossoudovitch

Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

2017

Improvement of the tolerated raw bit error rate in NAND flash-based SSDs with the help of embedded statistics.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2017

Refresh frequency reduction of data stored in SSDs based on A-timer and timestamps.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE European Test Symposium, 2017

2014

Error Correction Schemes with Erasure Information for Fast Memories.

[BibT_eX]

[DOI]

Valentin Savin

J. Electron. Test., 2014

Flip-flop selection for in-situ slack-time monitoring based on the activation probability of timing-critical paths.

[BibT_eX]

[DOI]

Sébastien Sarrazin

Lirida Alves de Barros Naviner

Ivan Miro Panades

Lirida Alves de Barros Naviner

Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Shadow-scan design with low latency overhead and in-situ slack-time monitoring.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE European Test Symposium, 2014

2013

Memory Reliability Improvement Based on Maximized Error-Correcting Codes.

[BibT_eX]

[DOI]

J. Electron. Test., 2013

Error-correction schemes with erasure information for fast memories.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE European Test Symposium, 2013

Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection.

[BibT_eX]

[DOI]

Sébastien Sarrazin

Lirida Alves de Barros Naviner

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Memory reliability improvements based on maximized error-correcting codes.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE European Test Symposium, 2012

2011

Programmable extended SEC-DED codes for memory errors.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Generalized parity-check matrices for SEC-DED codes with fixed parity.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Error prediction based on concurrent self-test and reduced slack time.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Programmable restricted SEC codes to mask permanent faults in semiconductor memories.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

2009

System-level hardware-based protection of memories against soft-errors.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

2007

Deterministic logic BIST for transition fault testing.

[BibT_eX]

[DOI]

Jürgen Schlöffel

Michael Garbers

IET Comput. Digit. Tech., 2007

Synthesis of irregular combinational functions with large don't care sets.

[BibT_eX]

[DOI]

R. D. Mascarenhas

Jürgen Schlöffel

Michael Garbers

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2005

Implementing a Scheme for External Deterministic Self-Test.

[BibT_eX]

[DOI]

Abdul Wahid Hakmi

Michael Garbers

Jürgen Schlöffel

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

2004

Efficient Pattern Mapping for Deterministic Logic BIST.

[BibT_eX]

[DOI]