Valentin Gherman
Orcid: 0009-0008-8322-9906
According to our database1,
Valentin Gherman
authored at least 25 papers
between 2004 and 2024.
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Bibliography
2024
IEEE J. Solid State Circuits, September, 2024
Proceedings of the 42nd IEEE VLSI Test Symposium, 2024
2023
Benefits of Design Assist Techniques on Performances and Reliability of a RRAM Macro.
Proceedings of the IEEE International Memory Workshop, 2023
2020
On Using Approximate Computing to Build an Error Detection Scheme for Arithmetic Circuits.
J. Electron. Test., 2020
Binary Linear ECCs Optimized for Bit Inversion in Memories with Asymmetric Error Probabilities.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2018
Evaluation of the temperature influence on SEU vulnerability of DICE and 6T-SRAM cells.
Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018
Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018
2017
Improvement of the tolerated raw bit error rate in NAND flash-based SSDs with the help of embedded statistics.
Proceedings of the IEEE International Test Conference, 2017
Proceedings of the 22nd IEEE European Test Symposium, 2017
2014
J. Electron. Test., 2014
Flip-flop selection for in-situ slack-time monitoring based on the activation probability of timing-critical paths.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Proceedings of the 19th IEEE European Test Symposium, 2014
2013
J. Electron. Test., 2013
Proceedings of the 18th IEEE European Test Symposium, 2013
Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection.
Proceedings of the Design, Automation and Test in Europe, 2013
2012
Proceedings of the 17th IEEE European Test Symposium, 2012
2011
Proceedings of the 29th IEEE VLSI Test Symposium, 2011
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
Proceedings of the Design, Automation and Test in Europe, 2011
2010
Programmable restricted SEC codes to mask permanent faults in semiconductor memories.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010
2009
Proceedings of the Design, Automation and Test in Europe, 2009
2007
IET Comput. Digit. Tech., 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
2005
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005
2004
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004