Valentin Egloff

According to our database, Valentin Egloff authored at least 8 papers between 2020 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Modeling Clock Glitch Fault Injection Effects on a RISC-V Microcontroller.

Ihab Alshaer, Ahmed Al-Kaf, Valentin Egloff, Vincent Beroulle

Proceedings of the 30th IEEE International Symposium on On-Line Testing and Robust System Design, 2024

Inferred Fault Models for RISC-V and Arm: A Comparative Study.

Ihab Alshaer, Ahmed Al-Kaf, Valentin Egloff, Vincent Beroulle

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2024

2022

Exploration and conception of computing architectures of type computing in-memory based on emerging non volatile memories. (Exploration et conception d'architectures de calcul de type in-memory à base de mémoires non volatiles émergentes).

Valentin Egloff

PhD thesis, 2022

Towards a Truly Integrated Vector Processing Unit for Memory-bound Applications Based on a Cost-competitive Computational SRAM Design Solution.

Maha Kooli, Antoine Heraud, Henri-Pierre Charles, Bastien Giraud, Roman Gauchi, Mona Ezzadeen, Kevin Mambu, Valentin Egloff, Jean-Philippe Noel

ACM J. Emerg. Technol. Comput. Syst., 2022

An Automated Design Methodology for Computational SRAM Dedicated to Highly Data-Centric Applications: Invited Paper.

A. Philippe, Lorenzo Ciampolini, A. Philippe, M. Gerbaud, M. Ramirez-Corrales, Valentin Egloff, Bastien Giraud, Jean-Philippe Noël

Proceedings of the 24th ACM/IEEE Workshop on System Level Interconnect Pathfinding, 2022

2021

Storage Class Memory with Computing Row Buffer: A Design Space Exploration.

Valentin Egloff, Jean-Philippe Noel, Maha Kooli, Bastien Giraud, Lorenzo Ciampolini, Roman Gauchi, César Fuguet Tortolero, Eric Guthmuller, Mathieu Moreau, Jean-Michel Portal

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Reconfigurable tiles of computing-in-memory SRAM architecture for scalable vectorization.

Roman Gauchi, Valentin Egloff, Maha Kooli, Jean-Philippe Noël, Bastien Giraud, Pascal Vivet, Subhasish Mitra, Henri-Pierre Charles

Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

Computational SRAM Design Automation using Pushed-Rule Bitcells for Energy-Efficient Vector Processing.

Jean-Philippe Noël, Valentin Egloff, Maha Kooli, Roman Gauchi, Jean-Michel Portal, Henri-Pierre Charles, Pascal Vivet, Bastien Giraud

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020