Valek Szwarc

According to our database, Valek Szwarc authored at least 6 papers between 1994 and 2010.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2010

Low Complexity Reconfigurable DSP Circuit Implementations Based on Common Sub-expression Elimination.

Huong Ho, Valek Szwarc, Tad A. Kwasniewski

J. Signal Process. Syst., 2010

2009

A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications.

Huong Ho, Valek Szwarc, Tad A. Kwasniewski

Int. J. Reconfigurable Comput., 2009

2006

A High Performance Soft Decision Viterbi Decoder for Wlan and Broadband Applications.

Abdul-Rafeeq Abdul-Shakoor, Valek Szwarc

Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006

1996

A High-Speed, Real-to-Quadrature Converter with Filtering and Decimation.

Luc Desormeaux, Valek Szwarc, John H. Lodge

Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

1994

A chip set for pipeline and parallel pipeline FFT architectures.

Valek Szwarc, Luc Desormeaux, Wilson Wong, Clifford P. S. Yeung, Chong H. Chan, Tad A. Kwasniewski

J. VLSI Signal Process., 1994

A floating-point systolic array processing element with serial communication and built-in self-test.

T. C. Davies, Dhamin Al-Khalili, Valek Szwarc

J. VLSI Signal Process., 1994