Valavan Manohararajah

According to our database, Valavan Manohararajah authored at least 11 papers between 1997 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

The Stratix™ 10 Highly Pipelined FPGA Architecture.

David M. Lewis, Gordon R. Chiu, Jeffrey Chromczak, David R. Galloway, Ben Gamsa, Valavan Manohararajah, Ian Milton, Tim Vanderhoek, John Van Dyken

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

2007

Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow.

Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown

IEEE Trans. Very Large Scale Integr. Syst., 2007

2006

Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping.

Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow.

Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown

Proceedings of the Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), 2006

Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs.

Gordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Adaptive FPGAs: High-Level Architecture and a Synthesis Method.

Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2005

Post-Placement BDD-Based Decomposition for FPGAs.

Valavan Manohararajah, Deshanand P. Singh, Stephen Dean Brown

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Incremental retiming for FPGA physical synthesis.

Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown

Proceedings of the 42nd Design Automation Conference, 2005

Two-stage physical synthesis for FPGAs.

Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2002

Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices.

Valavan Manohararajah, Terry P. Borer, Stephen Dean Brown, Zvonko G. Vranesic

Proceedings of the Field-Programmable Logic and Applications, 2002

1997

Rajah: The Design of a Chess Program.

Valavan Manohararajah

J. Int. Comput. Games Assoc., 1997