Val Pevzner

According to our database, Val Pevzner authored at least 7 papers between 2009 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2014

Rent's rule based FPGA packing for routability optimization.

Wenyi Feng, Jonathan W. Greene, Kristofer Vorwerk, Val Pevzner, Arun Kundu

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

2011

FPGA technology mapping with encoded libraries and staged priority cuts.

Andrew A. Kennings, Kristofer Vorwerk, Arun Kundu, Val Pevzner, Andy Fox

ACM Trans. Reconfigurable Technol. Syst., 2011

A 65nm flash-based FPGA fabric optimized for low cost and power.

Jonathan W. Greene, Sinan Kaptanoglu, Wenyi Feng, Volker Hecht, Joel Landry, Fei Li, Anton Krouglyanskiy, Mihai Morosan, Val Pevzner

Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

2010

Power minimisation during field programmable gate array placement.

Kristofer Vorwerk, Andrew A. Kennings, Val Pevzner, Arun Kundu, Madhu Raman, Julien Dunoyer, Yaun-shung Hsu

IET Comput. Digit. Tech., 2010

Efficient FPGA Resynthesis Using Precomputed LUT Structures.

Andrew A. Kennings, Alan Mishchenko, Kristofer Vorwerk, Val Pevzner, Arun Kundu

Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

2009

Physical optimization for FPGAs using post-placement topology rewriting.

Val Pevzner, Andrew A. Kennings, Andy Fox

Proceedings of the 2009 International Symposium on Physical Design, 2009

FPGA technology mapping with encoded libraries andstaged priority cuts.

Andrew A. Kennings, Kristofer Vorwerk, Arun Kundu, Val Pevzner, Andy Fox

Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009