Vaishnav Srinivas

Orcid: 0009-0009-7929-2520

According to our database1, Vaishnav Srinivas authored at least 15 papers between 2011 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Online presence:

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Bibliography

2022
SPROUT - Smart Power Routing Tool for Board-Level Exploration and Prototyping.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2021
SPROUT - Smart Power ROUting Tool for Board-Level Exploration and Prototyping.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
Cross-Layer Co-Optimization of Network Design and Chiplet Placement in 2.5-D Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Power Delivery Exploration Methodology Based on Constrained Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Graph-Based Power Network Routing for Board-Level High Performance Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Cross-Layer Pathfinding for Off-Chip Interconnects
PhD thesis, 2019

Learning-based prediction of package power delivery network quality.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
Versatile Framework for Power Delivery Exploration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A cross-layer methodology for design and optimization of networks in 2.5D systems.
Proceedings of the International Conference on Computer-Aided Design, 2018

2017
Adaptive Tuning of Photonic Devices in a Photonic NoC Through Dynamic Workload Allocation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

CACTI 7: New Tools for Interconnect Exploration in Innovative Off-Chip Memories.
ACM Trans. Archit. Code Optim., 2017

2016
Cross-layer floorplan optimization for silicon photonic NoCs in many-core systems.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
CACTI-IO: CACTI With OFF-Chip Power-Area-Timing Models.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Clock clustering and IO optimization for 3D integration.
Proceedings of the 2015 ACM/IEEE International Workshop on System Level Interconnect Prediction, 2015

2011
Mobile system considerations for SDRAM interface trends.
Proceedings of the 2011 International Workshop on System Level Interconnect Prediction, 2011


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